公开(公告)号：US20250113542A1

公开(公告)日：2025-04-03

申请号：US18887091

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU ,  Masahiro WATABE

IPC: H01L29/786

Abstract: A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.

公开(公告)号：US20250063761A1

公开(公告)日：2025-02-20

申请号：US18934397

申请日：2024-11-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/66 ,  H10K59/121

Abstract: A semiconductor device includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.

公开(公告)号：US20250022965A1

公开(公告)日：2025-01-16

申请号：US18898827

申请日：2024-09-27

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Toshinari SASAKI ,  Hajime WATAKABE ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device according to an embodiment includes: a metal oxide layer above a substrate, the metal oxide layer containing aluminum as a main component; an oxide semiconductor layer above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein the oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.

公开(公告)号：US20250022964A1

公开(公告)日：2025-01-16

申请号：US18760532

申请日：2024-07-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/423

Abstract: A semiconductor device comprises a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a gate wiring on the gate insulating layer, and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. The first region overlaps the gate insulating layer and the gate wiring. The third region is in contact with the second insulating layer. A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer.

公开(公告)号：US20250015198A1

公开(公告)日：2025-01-09

申请号：US18894269

申请日：2024-09-24

Applicant: Japan Display Inc. ,  IDEMITSU KOSAN CO., LTD.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Emi KAWASHIMA ,  Yuki TSURUMA ,  Daichi SASAKI

IPC: H01L29/786 ,  C01G15/00 ,  C23C14/08 ,  H01L29/66

Abstract: An oxide semiconductor film having crystallinity over a substrate contains indium (In) and a first metal element (M1). The oxide semiconductor film includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation , a crystal orientation , and a crystal orientation obtained by an electron backscatter diffraction (EBSD) method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation is greater than an occupancy rate of the crystal orientation and an occupancy rate of the crystal orientation .

公开(公告)号：US20240288739A1

公开(公告)日：2024-08-29

申请号：US18433729

申请日：2024-02-06

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/136295 ,  G02F1/13685 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1225

Abstract: An electronic device comprises a first stacked structure including a first oxide semiconductor layer having a polycrystalline structure, a first insulating layer on the first oxide semiconductor layer, and a first conductive layer overlapping the first oxide semiconductor layer via the first insulating layer; and a second stacked structure including a second oxide semiconductor layer composed of the same layer as the first oxide semiconductor layer, the first insulating layer on the second oxide semiconductor layer, and a second conductive layer overlapping the second oxide semiconductor layer via the first insulating layer and composed of the same layer as the first conductive layer. A portion of the first oxide semiconductor layer not overlapping the first conductive layer contains an impurity element, and the second oxide semiconductor layer does not contain the impurity element.

公开(公告)号：US20240128273A1

公开(公告)日：2024-04-18

申请号：US18393873

申请日：2023-12-22

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Toshihide JINNAI ,  Ryo ONODERA ,  Akihiro HANADA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1285 ,  H01L29/66742 ,  H01L29/7869

Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.

公开(公告)号：US20240069400A1

公开(公告)日：2024-02-29

申请号：US18503351

申请日：2023-11-07

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Toshihide JINNAI ,  Isao SUZUMURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  H10K50/86 ,  H10K59/131

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136277 ,  G02F1/136286 ,  H01L29/78633 ,  H01L29/78672 ,  H10K50/865 ,  H10K59/131

Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

公开(公告)号：US20230387146A1

公开(公告)日：2023-11-30

申请号：US18366859

申请日：2023-08-08

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Isao SUZUMURA ,  Akihiro HANADA ,  Yohei YAMAGUCHI

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1292 ,  H01L29/24 ,  H01L29/78666 ,  H01L29/7869 ,  H01L29/66969 ,  H01L27/1225 ,  H01L29/66757

Abstract: A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.

公开(公告)号：US20230317853A1

公开(公告)日：2023-10-05

申请号：US18328788

申请日：2023-06-05

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Tomoyuki ITO ,  Toshihide JINNAI ,  lsao SUZUMURA ,  Akihiro HANADA ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66

CPC classification number: H01L29/78627 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/7869 ,  H01L27/127 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/426 ,  H01L21/47573 ,  H01L21/47635 ,  H01L29/66969 ,  H01L27/1225 ,  G02F1/1368

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.