公开(公告)号：US20130175579A1

公开(公告)日：2013-07-11

申请号：US13347161

申请日：2012-01-10

申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

IPC分类号： H01L29/78 ,  H01L21/335

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

摘要： A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.

摘要翻译： 晶体管包括第一半导体层。 第二半导体层位于第一半导体层上。 去除第二半导体层的一部分以暴露第一半导体层的第一部分并提供第二半导体层的垂直侧壁。 栅极间隔物位于第二半导体层上。 栅极电介质包括位于第一半导体层的第一部分上的第一部分和与第二半导体层的垂直侧壁相邻的第二部分。 栅极导体位于栅极电介质的第一部分上并邻接栅极电介质第二部分。 沟道区位于第一半导体层的第一部分的至少一部分中。 上升的源极/漏极区域位于第二半导体层中。 凸起的源极/漏极区域的至少一部分位于栅极间隔物的下方。

公开(公告)号：US08440552B1

公开(公告)日：2013-05-14

申请号：US13346008

申请日：2012-01-09

申请人： Kangguo Chen ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

发明人： Kangguo Chen ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

IPC分类号： H01L21/225

CPC分类号： H01L21/2255 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636

摘要： A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.

摘要翻译： 一种方法包括提供具有半导体层的ETSOI晶片，所述半导体层具有顶表面，所述半导体层具有至少一个在其侧壁上具有介电材料层的栅极结构。 电介质材料层的一部分远离半导体层表面上的栅极结构延伸。 该方法还包括将邻近该介电材料层的部分的半导体层上的升高的S / D断开，去除介电材料层的该部分以暴露该半导体层表面的下面部分并施加一层 的含有掺杂剂的玻璃以至少覆盖半导体层的表面的暴露部分。 该方法还包括通过半导体层的表面的暴露部分扩散掺杂剂以形成源极延伸区域和漏极延伸区域。

公开(公告)号：US20130082308A1

公开(公告)日：2013-04-04

申请号：US13251757

申请日：2011-10-03

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

摘要翻译： 公开了晶体管器件及其制造方法。 在一种方法中，在基板上形成虚拟栅极结构。 虚拟门结构的底部是底切的。 此外，在基板上形成阶梯状，凸起的源极和漏极区域，以及由底切形成的至少一个底切部。 去除虚拟栅极结构并在衬底上形成替换栅极。

公开(公告)号：US08399957B2

公开(公告)日：2013-03-19

申请号：US13082491

申请日：2011-04-08

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L29/06

CPC分类号： H01L29/66742 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

摘要翻译： 通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。 将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。 氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。 将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。 在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

公开(公告)号：US20130034938A1

公开(公告)日：2013-02-07

申请号：US13611044

申请日：2012-09-12

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。

公开(公告)号：US08358012B2

公开(公告)日：2013-01-22

申请号：US12849390

申请日：2010-08-03

申请人： Balasubramanian S. Haran ,  Sivananda K. Kanakasabapathy

发明人： Balasubramanian S. Haran ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L29/40

CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

摘要翻译： 在覆盖半导体层的电介质材料层中蚀刻接触孔，以露出半导体层的最上表面。 接触通孔延伸到半导体材料层中，继续蚀刻半导体层，使得在半导体材料层中形成具有半导体侧壁的沟槽。 在电介质材料层和沟槽的侧壁和底表面上沉积金属层。 在高温退火时，形成金属半导体合金区域，其包括顶部金属半导体合金部分，其中包括空腔，底部金属半导体合金部分位于空腔下方并包括水平部分。 金属接触通孔形成在空腔内，使得顶部金属半导体合金部分横向地围绕金属接触通孔的底部的底部。

公开(公告)号：US20130015525A1

公开(公告)日：2013-01-17

申请号：US13179990

申请日：2011-07-11

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Balasubramanian S. Haran

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/0332 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656

摘要： An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

公开(公告)号：US20120187482A1

公开(公告)日：2012-07-26

申请号：US13013801

申请日：2011-01-25

申请人： Lahir S. Adam ,  Sanjay C. Mehta ,  Balasubramanian S. Haran ,  Bruce B. Doris

发明人： Lahir S. Adam ,  Sanjay C. Mehta ,  Balasubramanian S. Haran ,  Bruce B. Doris

IPC分类号： H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4983 ,  H01L29/7843

摘要： CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

摘要翻译： 形成CMOS晶体管，其结合有在n沟道场效应晶体管的栅极侧壁上具有紧张应力间隔物的栅极，并且在ap沟道场效应晶体管的栅极侧壁上具有压缩应力间隔物，以在相应晶体管中提供差分应力通道以增加载流子迁移率 在各自的频道。

公开(公告)号：US08987070B2

公开(公告)日：2015-03-24

申请号：US13611182

申请日：2012-09-12

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66772 ,  H01L29/78654

摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。

公开(公告)号：US08889564B2

公开(公告)日：2014-11-18

申请号：US13600324

申请日：2012-08-31

申请人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。