公开(公告)号：US09619231B2

公开(公告)日：2017-04-11

申请号：US14200417

申请日：2014-03-07

Applicant: Microchip Technology Incorporated

Inventor： Michael I. Catherwood ,  Bryan Kris ,  David Mickey ,  Joseph Kanellopoulos

IPC: G06F9/30 ,  G06F9/46 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3009 ,  G06F9/3865 ,  G06F9/462

Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

公开(公告)号：US20160344289A1

公开(公告)日：2016-11-24

申请号：US15157879

申请日：2016-05-18

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  James Bartling

IPC: H02M3/156 ,  H03M1/12 ,  H02M1/08 ,  H03G3/20 ,  H03F3/45

CPC classification number: H02M3/156 ,  G01R19/003 ,  G01R19/255 ,  H02M1/08 ,  H02M2001/0009 ,  H03F3/45 ,  H03F2203/45288 ,  H03G3/20 ,  H03M1/1245

Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.

Abstract translation: 可以通过首先将复波形转换为电压，然后将该电压转换成电流并使用该电流来对电容器充电来确定在一段时间内测量的复波形的平均值。 在测量时间段结束时，电容器上的电压（采样电压）可以通过与模数转换器（ADC）相关联的采样和保持电路进行采样。 然后可以去除样品电容器上的电荷电荷，例如电容器板由转储开关短路，以准备复杂波形采样测量周期的下一个平均值。 然后，ADC将该采样的电压电荷转换成其数字表示，并且可以结合测量时间周期来确定复数波形的真实平均值，例如从其计算。

公开(公告)号：US20160231376A1

公开(公告)日：2016-08-11

申请号：US15012287

申请日：2016-02-01

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G06F11/0772 ,  G01R31/2851 ,  G01R31/3177 ,  G06F11/2231 ,  G06F11/3648 ,  G06F11/3652

Abstract: In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

Abstract translation: 在具有多个处理核心的集成电路装置的调试方法中，在集成电路装置的第一处理器核心处激活调试断点。 在激活时，调试断点停止执行第一处理器核心中的指令，并且将调试断点传送到集成电路设备中的第二处理器核心。

公开(公告)号：US20160094193A1

公开(公告)日：2016-03-31

申请号：US14863779

申请日：2015-09-24

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  James E. Bartling

IPC: H03G1/00 ,  H03F3/45 ,  H03G3/00

CPC classification number: H03G1/0088 ,  H03F3/45475 ,  H03F2200/321 ,  H03F2203/45048 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45616 ,  H03F2203/45728 ,  H03G3/001

Abstract: An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.

Abstract translation: 可配置为可编程增益放大器或运算放大器的集成电路放大器包括两个输出块，一个输出块针对可编程增益放大器操作进行了优化，另一个输出块针对运算放大器应用进行了优化。 使用常见的单输入级，输入偏移校准和偏置生成电路与放大器配置。 因此，消除了输入级，偏移校准和偏置产生电路的复制，同时仍然可选地提供可编程增益放大器或运算放大器配置。

公开(公告)号：US20150356037A1

公开(公告)日：2015-12-10

申请号：US14729879

申请日：2015-06-03

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Bryan Kris

IPC: G06F13/28 ,  G06F13/38

CPC classification number: G06F13/287 ,  G06F13/385 ,  G06F15/7814 ,  H03K19/1732

Abstract: An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device has an output. Furthermore, a housing with a plurality of assignable external pins and a protected pin ownership logic for each assignable external pin is provided and configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores.

Abstract translation: 嵌入式设备具有多个处理器核心，每个处理器核心具有多个外围设备，其中每个外围设备具有输出。 此外，提供具有多个可分配外部引脚的外壳和用于每个可分配的外部引脚的受保护的引脚所有权逻辑，并将其配置为可编程以将相关联的可分配外部引脚的输出功能分配给多个处理器核心中的一个。

公开(公告)号：US20150019847A1

公开(公告)日：2015-01-15

申请号：US14200417

申请日：2014-03-07

Applicant: Microchip Technology Incorporated

Inventor： Michael I. Catherwood ,  Bryan Kris ,  David Mickey ,  Joseph Kanellopoulos

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3009 ,  G06F9/3865 ,  G06F9/462

Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

Abstract translation: 具有用于中断执行指令的中断单元的中央处理单元（CPU），多个上下文定义寄存器组，其中每组具有相同数目的CPU寄存器的寄存器，用于耦合所选择的CPU内的寄存器组的切换单元， 其中所述切换单元在出现异常时切换到所述多个上下文定义寄存器组的预定寄存器组，以及控制寄存器，其被配置为控制由指令启动的所述多个上下文定义寄存器的寄存器组的选择，并且还可操作 以指示当前使用的上下文。

公开(公告)号：US08866525B2

公开(公告)日：2014-10-21

申请号：US13778436

申请日：2013-02-27

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  John Day ,  Alex Dumais ,  Stephen Bowling

IPC: H03K3/017 ,  H03K5/13

CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

公开(公告)号：US20200059239A1

公开(公告)日：2020-02-20

申请号：US16534199

申请日：2019-08-07

Applicant: Microchip Technology Incorporated

Inventor： Neil Deutscher ,  Bryan Kris

IPC: H03M1/50 ,  H03M1/12 ,  H03M1/16

Abstract: An analog to digital converter (ADC) includes voltage inputs, a transconductor configured to convert the voltage inputs into currents, current-controlled oscillators, a counter, and digital logic. The current-controlled oscillators propagate respect currents from the transconductor. The counter is configured to count repeated traversal of one or more oscillators. The digital logic is configured to, based upon results from the counter, provide a code configured to indicate a value of associated voltage input.

公开(公告)号：US20180183453A1

公开(公告)日：2018-06-28

申请号：US15901294

申请日：2018-02-21

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: H03M1/10 ,  H03M1/38 ,  H03K5/131 ,  H03K5/14 ,  H03K5/00

CPC classification number: H03M1/34 ,  H02M3/156 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

Abstract: Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

公开(公告)号：US09923570B2

公开(公告)日：2018-03-20

申请号：US15485020

申请日：2017-04-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher ,  Thomas S. Spohrer

IPC: H03M1/34 ,  H03M1/10 ,  H03K5/14 ,  H03K5/131 ,  H03K5/00

CPC classification number: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.