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    METHODS OF FORMING MEMORY CELLS WITH AIR GAPS AND OTHER LOW DIELECTRIC CONSTANT MATERIALS
    51.
    发明申请
    METHODS OF FORMING MEMORY CELLS WITH AIR GAPS AND OTHER LOW DIELECTRIC CONSTANT MATERIALS 有权
    用空气GAPS和其他低介电常数材料形成记忆细胞的方法

    公开(公告)号：US20160254159A1

    公开(公告)日：2016-09-01

    申请号：US15154467

    申请日：2016-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Minsoo Lee ,  Akira Goda

    IPC: H01L21/28 ,  H01L21/764 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7889

    Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

    Abstract translation: 各种实施例包括其形成装置和方法。 一种这样的设备可以包括第一介电材料和第二介电材料，以及在第一介电材料和第二介电材料之间的导电材料。 诸如浮动栅极或电荷阱的电荷存储元件位于第一介电材料和第二电介质材料之间并且与导电材料相邻。 电荷存储元件具有第一表面和第二表面。 第一和第二表面分别通过第一气隙和第二气隙与第一介电材料和第二电介质材料分开。 公开了附加的装置和方法。

    Methods of forming memory cells with air gaps and other low dielectric constant materials
    52.
    发明授权
    Methods of forming memory cells with air gaps and other low dielectric constant materials 有权
    用气隙和其他低介电常数材料形成记忆体的方法

    公开(公告)号：US09343316B2

    公开(公告)日：2016-05-17

    申请号：US14825947

    申请日：2015-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Minsoo Lee ,  Akira Goda

    IPC: H01L27/115 ,  H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/788 ,  H01L29/423

    CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7889

    Abstract: Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a substrate. A conductive material is formed between the first dielectric material and the second dielectric material. An opening is formed through the first dielectric material, the second dielectric material, and the conductive material. The conductive material is recessed laterally from the opening to form a recessed control gate and to expose portions of the first dielectric material and the second dielectric material. Portions of a third dielectric material are formed over the exposed portions of the first dielectric material and the second dielectric material and a charge storage element is formed between the portions of the third dielectric material and adjacent to the recessed control gate. Portions of the third dielectric material are substantially removed. Additional methods, as well as apparatuses, are disclosed.

    Abstract translation: 各种实施例包括形成存储器单元的方法。 在一个实施例中，在基板上形成第一电介质材料和第二电介质材料。 在第一介电材料和第二电介质材料之间形成导电材料。 通过第一介电材料，第二介电材料和导电材料形成开口。 导电材料从开口侧向凹入以形成凹入的控制栅极并暴露第一介电材料和第二介电材料的部分。 在第一介电材料和第二介电材料的暴露部分上形成第三电介质材料的一部分，并且电荷存储元件形成在第三电介质材料的部分之间并与凹陷控制栅极相邻。 基本上去除了第三绝缘材料的部分。 公开了附加的方法以及装置。

    Memories and methods of programming memories
    53.
    发明授权
    Memories and methods of programming memories 有权
    记忆和程序记忆的方法

    公开(公告)号：US09105337B2

    公开(公告)日：2015-08-11

    申请号：US14199304

    申请日：2014-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

    IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459

    Abstract: Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.

    Abstract translation: 公开了用于调整存储器上部页面编程的装置和方法。 在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

    Apparatuses and methods to control body potential in memory operations
    55.
    发明授权
    Apparatuses and methods to control body potential in memory operations 有权
    在记忆操作中控制身体潜力的装置和方法

    公开(公告)号：US09064577B2

    公开(公告)日：2015-06-23

    申请号：US13707067

    申请日：2012-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  G11C16/16

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。

    Memory for programming data states of memory cells
    58.
    发明授权
    Memory for programming data states of memory cells 有权

    公开(公告)号：US12293790B2

    公开(公告)日：2025-05-06

    申请号：US17894248

    申请日：2022-08-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Koichi Kawai ,  Yoshihiko Kamata ,  Akira Goda

    IPC: G11C16/10 ,  G11C7/10 ,  G11C16/34 ,  H03K19/017

    Abstract: Memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.

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