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    Methods for detecting and mitigating memory media degradation and memory devices employing the same
    51.
    发明授权
    Methods for detecting and mitigating memory media degradation and memory devices employing the same 有权

    公开(公告)号：US10475519B2

    公开(公告)日：2019-11-12

    申请号：US15933678

    申请日：2018-03-23

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan S. Parry ,  George B. Raad ,  James S. Rehmeyer ,  Timothy B. Cowles

    IPC: G11C7/00 ,  G11C16/34 ,  G11C11/406

    Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

    DATA MOVEMENT OPERATIONS IN NON-VOLATILE MEMORY
    53.
    发明申请
    DATA MOVEMENT OPERATIONS IN NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20190171558A1

    公开(公告)日：2019-06-06

    申请号：US15831698

    申请日：2017-12-05

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  Timothy B. Cowles

    IPC: G06F12/02 ,  G06F3/06 ,  G11C16/10 ,  G11C7/06 ,  G11C29/52 ,  G06F11/10

    Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.

    Apparatuses and methods for compressing data received over multiple memory accesses
    54.
    发明授权
    Apparatuses and methods for compressing data received over multiple memory accesses 有权
    用于压缩通过多个存储器访问接收的数据的装置和方法

    公开(公告)号：US09183952B2

    公开(公告)日：2015-11-10

    申请号：US13771838

    申请日：2013-02-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： James S. Rehmeyer ,  John F. Schreck ,  Timothy B. Cowles

    IPC: G11C29/40 ,  G11C29/44 ,  G11C29/48 ,  G11C29/00 ,  G06F11/07 ,  G01R31/317 ,  G01R31/3187 ,  G01R31/319 ,  G01R31/3193 ,  G11C29/56

    CPC classification number: G11C29/40 ,  G01R31/31703 ,  G01R31/3187 ,  G01R31/3193 ,  G01R31/31932 ,  G01R31/31935 ,  G06F11/076 ,  G11C29/44 ,  G11C29/48 ,  G11C29/70 ,  G11C2029/4002 ,  G11C2029/5606

    Abstract: Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator configured to compare data provided by a group of memory cells associated with a repair address. Each subset of one or more bits of the data is sequentially provided by the group of memory cells responsive to a respective memory access of a plurality of memory accesses. The example compression circuit further including an error bit latch coupled to the comparison circuit. The error bit latch configured to, responsive to an output received from the comparison circuit indicating an error, compress the data to an error bit by setting the error bit to an error detected state and latching the error bit having the error detected state.

    Abstract translation: 描述了响应于多个存储器访问来压缩数据的装置和方法。 示例压缩电路包括比较器，其被配置为比较由与修复地址相关联的一组存储器单元提供的数据。 响应于多个存储器访问的相应存储器访问，由该组存储器单元顺序地提供数据的一个或多个位的每个子集。 示例压缩电路还包括耦合到比较电路的错误位锁存器。 错误位锁存器被配置为响应于从比较电路接收的指示错误的输出，通过将错误位设置为错误检测状态并锁存具有错误检测状态的错误位来将数据压缩到错误位。

    DELAY OF INITIALIZATION AT MEMORY DIE
    55.
    发明申请
    DELAY OF INITIALIZATION AT MEMORY DIE 有权

    公开(公告)号：US20250044965A1

    公开(公告)日：2025-02-06

    申请号：US18920190

    申请日：2024-10-18

    Applicant: Micron Technology, Inc.

    Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

    IPC: G06F3/06 ,  G11C5/06 ,  G11C17/16

    Abstract: Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

    Selectable fuse sets, and related methods, devices, and systems
    57.
    发明授权
    Selectable fuse sets, and related methods, devices, and systems 有权

    公开(公告)号：US11869620B2

    公开(公告)日：2024-01-09

    申请号：US17647508

    申请日：2022-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

    IPC: G11C29/00 ,  G11C11/408

    CPC classification number: G11C29/70 ,  G11C11/4082

    Abstract: Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.

    Delay of self-refreshing at memory die
    59.
    发明授权
    Delay of self-refreshing at memory die 有权

    公开(公告)号：US11710514B2

    公开(公告)日：2023-07-25

    申请号：US17493501

    申请日：2021-10-04

    Applicant: Micron Technology, Inc.

    Inventor： Christopher D. Wieduwilt ,  Lawrence D. Smith ,  James S. Rehmeyer

    IPC: G11C11/406 ,  G11C17/16 ,  G11C11/4076

    CPC classification number: G11C11/40622 ,  G11C11/4076 ,  G11C11/40615 ,  G11C17/16

    Abstract: First signaling indicative of instructions to enter a self-refresh (SREF) mode can be received concurrently by a plurality of memory dies. Responsive to a memory die of the plurality of memory dies entering the SREF mode, self-refreshing of memory banks of the memory die can be delayed, at the memory die and based on fuse states of an array of fuses of the memory die, an amount of time relative to receipt of the signaling by the memory die. Delaying self-refreshing of memory banks of memory dies in a staggered, or asynchronous, manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

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