公开(公告)号：US20160111167A1

公开(公告)日：2016-04-21

申请号：US14518727

申请日：2014-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

IPC: G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

Abstract translation: 本文描述了用于减少读取干扰的装置和方法。 示例性装置可以包括包括第一选择栅极漏极（SGD）开关和第一选择栅极源（SGS）开关的第一存储器子块，包括第二SGD开关和第二SGS开关的第二存储器子块以及与之相关联的存取线 与第一和第二存储器子块。 该装置可以包括控制单元，其被配置为在读取操作的第一部分期间使第一和第二SGD开关以及第一和第二SGS开关能够实现，并且在第一部分期间在存取线上提供第一电压。 控制单元可以被配置为在读取操作的第二部分期间禁用第一SGD开关和第一SGS开关，并且在第二部分期间在接入线上提供第二电压。

公开(公告)号：US09251860B2

公开(公告)日：2016-02-02

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C16/00 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

公开(公告)号：US09070442B2

公开(公告)日：2015-06-30

申请号：US14013370

申请日：2013-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C16/00 ,  G11C16/02 ,  G11C11/063 ,  G11C11/06 ,  G11C5/02

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

公开(公告)号：US11749349B2

公开(公告)日：2023-09-05

申请号：US17873216

申请日：2022-07-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C16/10 ,  G11C7/10 ,  G11C16/04 ,  H03K19/00 ,  G11C16/26 ,  H03K19/0185 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C16/10 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H03K19/0005 ,  H03K19/018528 ,  G11C2207/2254

Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

公开(公告)号：US11605418B2

公开(公告)日：2023-03-14

申请号：US17080310

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C13/00 ,  G11C11/408 ,  G11C11/4091

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US11210011B2

公开(公告)日：2021-12-28

申请号：US16691890

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Ramin Ghodsi

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804

Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

公开(公告)号：US20210383876A1

公开(公告)日：2021-12-09

申请号：US17408774

申请日：2021-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02

Abstract: Memory having a controller configured to cause the memory to determine a respective raw data value of a plurality of possible raw data values for each memory cell of a plurality of memory cells, count occurrences of each raw data value for a first set of memory cells of the plurality of memory cells, store a cumulative number of occurrences for each raw data value, determine a plurality of valleys of the stored cumulative number of occurrences for each raw data value with each valley corresponding to a respective raw data value of the plurality of possible raw data values, and, for each memory cell of a second set of memory cells of the plurality of memory cells, determine a data value for that memory cell in response to the raw data value for that memory cell and the respective raw data values of the plurality of valleys.

公开(公告)号：US11056201B2

公开(公告)日：2021-07-06

申请号：US17095291

申请日：2020-11-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Ramin Ghodsi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Memory might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to increase a voltage level applied to each of the access lines, determine a particular voltage level at which each memory cell of a first set of strings of memory cells is deemed to be activated while increasing the voltage level applied to the access lines, decrease the voltage level applied to a particular access line without decreasing the voltage level applied to each remaining access line, and, for each memory cell connected to the particular access line and contained in a second set of strings of memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.

公开(公告)号：US10854295B2

公开(公告)日：2020-12-01

申请号：US16178989

申请日：2018-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C16/10 ,  G11C16/04 ,  H03K19/00 ,  G11C16/26 ,  H03K19/0185 ,  G11C29/02 ,  G11C29/50 ,  G11C7/10

Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

公开(公告)号：US20200321065A1

公开(公告)日：2020-10-08

申请号：US16908832

申请日：2020-06-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Ramin Ghodsi

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.