公开(公告)号：US06420746B1

公开(公告)日：2002-07-16

申请号：US09182857

申请日：1998-10-29

申请人： John A. Bracchitta ,  Randy W. Mann ,  Jeffrey H. Oppold

发明人： John A. Bracchitta ,  Randy W. Mann ,  Jeffrey H. Oppold

IPC分类号： H01L27108

CPC分类号： H01L27/108 ,  H01L21/76895 ,  H01L28/40

摘要： A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.

摘要翻译： 一种半导体集成电路存储单元，包括至少三个晶体管和用于形成DRAM的电容器。 存储单元制造在包括杂质区域的半导体衬底上，并且在半导体膜之间使用两个半导体膜和介电膜。 电容器包含两个电极。 衬底杂质区形成电极之一; 另一个电极是将一个器件的栅极连接到另一个器件的杂质区域的半导体膜。 还公开了可用于制造类似电路的上述集成电路的制造方法。

公开(公告)号：US06338921B1

公开(公告)日：2002-01-15

申请号：US09479150

申请日：2000-01-07

申请人： James A. Bruce ,  David V. Horak ,  Randy W. Mann ,  Jed H. Rankin ,  Andrew J. Watts

发明人： James A. Bruce ,  David V. Horak ,  Randy W. Mann ,  Jed H. Rankin ,  Andrew J. Watts

IPC分类号： G03F102

CPC分类号： G03F7/0035 ,  G03F1/36

摘要： A mask (50′) with linewidth compensation and a method of making same. The mask provides for optimized imaging of isolated patterns (64) and nested patterns (70) present on the same mask. The compensated mask is formed from an uncompensated mask (50) and comprises an upper surface (56) upon which the isolated and nested patterns are formed. The isolated pattern comprises a first segment (76) having first sidewalls (76S). The nested pattern comprises second segments (72) proximate each other and having second sidewalls (72S). A partial conformal layer (86) covers the first segment and has feet (90) outwardly extending a distance d from the first sidewalls along the upper surface. The feet are preferably of a thickness that partially transmits exposure light.

摘要翻译： 具有线宽补偿的掩模（50'）及其制造方法。 掩模提供对同一掩模上存在的孤立图案（64）和嵌套图案（70）的优化成像。 补偿掩模由未补偿的掩模（50）形成，并且包括形成隔离和嵌套图案的上表面（56）。 隔离图案包括具有第一侧壁（76S）的第一段（76）。 嵌套图案包括彼此靠近并具有第二侧壁（72S）的第二段（72）。 部分保形层（86）覆盖第一段并且具有沿着上表面向外延伸距离第一侧壁的距离d的脚（90）。 脚部优选地具有部分地透射曝光光的厚度。

公开(公告)号：US06187617B1

公开(公告)日：2001-02-13

申请号：US09363558

申请日：1999-07-29

申请人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Randy W. Mann ,  Steven H. Voldman

IPC分类号： H01L21336

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/456

摘要： A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited over the semiconductor substrate (10). The semiconductor substrate (10) is annealed at a temperature between approximately 600° C. and approximately 700° C. During the annealing process, the titanium deposited in areas outside the molybdenum regions (73, 74, 75, 76) interacts with silicon on the substrate to form titanium silicide in a high resistivity C49 crystal phase. The titanium deposited in areas within the molybdenum regions (73, 74, 75, 76) interacts with silicon to form titanium silicide in a low resistivity C54 crystal phase because the presence of molybdenum ions in silicon lowers the energy barrier for crystal phase transformation between the C49 phase and the C54 phase.

摘要翻译： 在半导体衬底（10）上形成异质硅化物结构的方法包括将钼离子注入到半导体衬底（10）的选择区域中以形成钼区（73,74,75,76）。 然后将钛沉积在半导体衬底（10）上。 半导体衬底（10）在大约600℃和大约700℃之间的温度下退火。在退火过程中，沉积在钼区域（73,74,75,76）之外的区域中的钛与硅 该基板在高电阻率C49晶相中形成硅化钛。 在钼区域（73,74,75,76）中的区域中沉积的钛与硅相互作用以在低电阻率C54晶体相中形成硅化钛，因为硅中的钼离子的存在降低了能量势垒以进行晶体相变 C49相和C54相。

公开(公告)号：US08947912B2

公开(公告)日：2015-02-03

申请号：US13810728

申请日：2011-07-20

申请人： Benton H. Calhoun ,  Randy W. Mann

发明人： Benton H. Calhoun ,  Randy W. Mann

IPC分类号： G11C11/00 ,  H01L21/70 ,  G11C11/412 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/768 ,  Y10S257/903

摘要： Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors.

摘要翻译： 使用包括单向栅极导体的交叉耦合反相器来描述存储器单元。 用于存取晶体管的栅极导体也可以与逆变器栅极导体的长轴对准。 交叉耦合对中的一个逆变器的触点可以与另一个逆变器的栅极导体的长轴对准。 单独形成的矩形有源区域可以跨越上拉，下拉和存取晶体管与栅极导体正交。 可以形成单独的有源区域，使得与存取晶体管和/或上拉晶体管相关联的有源区域与与反相器的下拉晶体管相关联的有源区域不连续并且窄于与下拉晶体管的下拉晶体管相关联的有源区域。 6T SRAM和类似的存储单元拓扑的主要部件可以基本上由矩形线阵列形成，包括单向栅极导体和触点，以及与逆变器和存取晶体管交叉的栅极导体的单向矩形有源区。

公开(公告)号：US20130332136A1

公开(公告)日：2013-12-12

申请号：US13490096

申请日：2012-06-06

申请人： Bipul C. Paul ,  Randy W. Mann ,  Anurag Mittal

发明人： Bipul C. Paul ,  Randy W. Mann ,  Anurag Mittal

IPC分类号： G06G7/62

CPC分类号： G06F17/5063 ,  G06F17/5036

摘要： A method includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result.

摘要翻译： 一种方法包括指定包括多个晶体管的存储单元的单元不匹配参数以及多个晶体管中的每一个的晶体管失配参数的初始值。 基于计算装置中的晶体管失配参数，为多个晶体管中的每一个确定临界电流灵敏度参数。 单元不匹配参数分布在计算设备中的多个晶体管上，以基于临界电流灵敏度参数和单元不匹配参数来更新多个晶体管中的每一个的各个晶体管失配参数。 基于单个晶体管失配参数来模拟存储单元以产生模拟结果。

公开(公告)号：US20130293250A1

公开(公告)日：2013-11-07

申请号：US13462942

申请日：2012-05-03

申请人： William McMahon ,  Richard Francis ,  Randy W. Mann

发明人： William McMahon ,  Richard Francis ,  Randy W. Mann

IPC分类号： G01R31/3187

CPC分类号： G01R31/30 ,  G11C11/41 ,  G11C29/06

摘要： An integrated circuit device includes at least one test device and a stress generator coupled to the test device and operable to cycle the at least one test device to generate an AC stress. A method for testing an integrated circuit device including at least one test device and a stress generator coupled to the test device includes enabling the stress generator to cycle the at least one test device to generate an AC stress and measuring at least one parameter of the test device to determine an effect of the AC stress.

摘要翻译： 集成电路装置包括耦合到测试装置的至少一个测试装置和应力发生器，并可操作以循环至少一个测试装置以产生AC应力。 一种用于测试包括耦合到测试装置的至少一个测试装置和应力发生器的集成电路装置的方法，包括使所述应力发生器能够循环所述至少一个测试装置以产生AC应力并测量所述测试的至少一个参数 确定AC应力的作用的装置。

公开(公告)号：US20130242645A1

公开(公告)日：2013-09-19

申请号：US13810728

申请日：2011-07-20

申请人： Benton H. Calhoun ,  Randy W. Mann

发明人： Benton H. Calhoun ,  Randy W. Mann

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/768 ,  Y10S257/903

摘要： Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors.

摘要翻译： 使用包括单向栅极导体的交叉耦合反相器来描述存储器单元。 用于存取晶体管的栅极导体也可以与逆变器栅极导体的长轴对准。 交叉耦合对中的一个逆变器的触点可以与另一个逆变器的栅极导体的长轴对准。 单独形成的矩形有源区域可以跨越上拉，下拉和存取晶体管与栅极导体正交。 可以形成单独的有源区域，使得与存取晶体管和/或上拉晶体管相关联的有源区域与与反相器的下拉晶体管相关联的有源区域不连续并且窄于与下拉晶体管的下拉晶体管相关联的有源区域。 6T SRAM和类似的存储单元拓扑的主要部件可以基本上由矩形线阵列形成，包括单向栅极导体和触点，以及与反相器和存取晶体管交叉的栅极导体的单向矩形有源区。

公开(公告)号：US20110092056A1

公开(公告)日：2011-04-21

申请号：US12977134

申请日：2010-12-23

申请人： Gregory Costrini ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Randy W. Mann

发明人： Gregory Costrini ,  Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Randy W. Mann

IPC分类号： H01L21/762 ,  H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1203

摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.

摘要翻译： 公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。 在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。 导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

公开(公告)号：US07193262B2

公开(公告)日：2007-03-20

申请号：US10905094

申请日：2004-12-15

申请人： Herbert L. Ho ,  John E. Barth, Jr. ,  Ramachandra Divakaruni ,  Wayne F. Ellis ,  Johnathan E. Faltermeier ,  Brent A. Anderson ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Randy W. Mann ,  Paul C. Parries

发明人： Herbert L. Ho ,  John E. Barth, Jr. ,  Ramachandra Divakaruni ,  Wayne F. Ellis ,  Johnathan E. Faltermeier ,  Brent A. Anderson ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Randy W. Mann ,  Paul C. Parries

IPC分类号： H01L29/94 ,  H01L29/00

CPC分类号： H01L27/0805 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US07166904B2

公开(公告)日：2007-01-23

申请号：US10708023

申请日：2004-02-03

申请人： Jason P. Gill ,  Terence B. Hook ,  Randy W. Mann ,  William J. Murphy ,  William R. Tonti ,  Steven H. Voldman

发明人： Jason P. Gill ,  Terence B. Hook ,  Randy W. Mann ,  William J. Murphy ,  William R. Tonti ,  Steven H. Voldman

IPC分类号： H01L29/00

CPC分类号： H01L27/11 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/7304 ,  H01L29/7378 ,  H01L29/7391 ,  H01L29/78 ,  Y10S257/903 ,  Y10S257/904

摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

摘要翻译： 一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。 电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。 在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。 电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。 本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。