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92 条记录 (耗时 0.056 秒)

    System and method for limiting exposure of hardware failure information for a secured execution environment
    56.
    发明授权
    System and method for limiting exposure of hardware failure information for a secured execution environment 有权
    用于限制安全执行环境的硬件故障信息暴露的系统和方法

    公开(公告)号：US07934076B2

    公开(公告)日：2011-04-26

    申请号：US10956322

    申请日：2004-09-30

    申请人： Stephen A. Fischer ,  Shamanna M. Datta

    发明人： Stephen A. Fischer ,  Shamanna M. Datta

    IPC分类号： G06F9/00

    CPC分类号： G06F21/74 ,  G06F2221/2101

    摘要： A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.

    摘要翻译： 描述了用于限制硬件故障信息的暴露的方法和装置。 在一个实施例中，处理器的错误报告系统可以将各种状态和错误地址数据记录到通过热复位事件保留其内容的寄存器中。 但是处理器的错误报告系统然后可以确定处理器是否以可信任或安全模式操作。 如果没有，则处理器的体系结构状态变量也可能被记录到寄存器中。 但是，如果处理器以可信任或安全模式运行，则可能会禁止对架构状态变量的日志记录或标记为无效。

    CLFLUSH micro-architectural implementation method and system
    58.
    发明授权
    CLFLUSH micro-architectural implementation method and system 有权
    CLFLUSH微架构实现方法和系统

    公开(公告)号：US06546462B1

    公开(公告)日：2003-04-08

    申请号：US09475759

    申请日：1999-12-30

    申请人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran

    发明人： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran

    IPC分类号： G06F1200

    CPC分类号： G06F12/0811 ,  G06F12/0804

    摘要： A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

    摘要翻译： 一种用于从一致性域中的所有高速缓存中刷新与线性存储器地址相关联的高速缓存行的系统和方法。 高速缓存控制器接收存储器地址，并且确定存储器地址是否存储在相干域中最接近的高速缓冲存储器中。 如果缓存行存储内存地址，则从缓存中刷新。 刷新指令被分配给高速缓存控制器内的写入组合缓冲器。 写合成缓冲器将信息发送到总线控制器。 总线控制器定位存储在相干域内的外部和英特尔高速缓存存储器中的存储器地址的实例; 这些实例被刷新。 然后可以从写入组合缓冲器中逐出驱动刷新指令。 控制位可以用于指示是否将写入组合缓冲器分配给闪存指令，存储器地址是否存储在最接近的高速缓冲存储器中，以及是否应该从写入组合缓冲器中驱逐刷新指令。

    Method and apparatus for multiplying and accumulating complex numbers in a digital filter
    59.
    发明授权
    Method and apparatus for multiplying and accumulating complex numbers in a digital filter 有权
    用于在数字滤波器中乘法和累加复数的方法和装置

    公开(公告)号：US06470370B2

    公开(公告)日：2002-10-22

    申请号：US09760969

    申请日：2001-01-16

    申请人： Stephen A. Fischer ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  Carole Dulong ,  Eiichi Kowashi

    发明人： Stephen A. Fischer ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  Carole Dulong ,  Eiichi Kowashi

    IPC分类号： G06F752

    CPC分类号： G06F17/10

    摘要： The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop). Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number. These eight data elements were previously stored as packed data and include two representations of each of the components of the current complex coefficient and its current corresponding data sample. Each of these data elements is either the positive or negative of the component they represent. As a result of the manner in which these eight data elements are stored, the currently calculated complex number represents the product of the current complex coefficient and its current corresponding data sample. The currently calculated complex number is then added to the current output packed data.

    摘要翻译： 本发明提供一种用于执行复杂数字滤波器的方法和装置。 根据本发明的一个方面，描述了一种用于执行复数数字滤波器的方法。 使用一组数据样本和一组复系数来执行复数数字滤波器。 另外，使用内循环和外循环执行复数数字滤波器。 外循环遍历复系数集合和数据样本集之间的若干对应关系。 内循环遍及复系数集合中的每个复系数。 在内循环中，根据当前对应关系（当前由外循环确定的对应关系）确定对应于当前复系数（由内循环确定的复系数）的数据样本。 然后，响应于接收到指令，读取并使用八个数据元素来生成当前计算的复数。 这八个数据元素预先存储为打包数据，并且包括当前复系数及其当前相应数据样本的每个分量的两个表示。 这些数据元素中的每一个都是它们表示的组件的正或负。 作为存储这八个数据元素的方式的结果，当前计算的复数代表当前复系数和其当前相应数据样本的乘积。 然后将当前计算的复数加到当前输出的打包数据中。