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    Efficient memory controller with an independent clock
    52.
    发明授权
    Efficient memory controller with an independent clock 失效
    具有独立时钟的高效存储控制器

    公开(公告)号：US5239639A

    公开(公告)日：1993-08-24

    申请号：US611183

    申请日：1990-11-09

    申请人： Stephen A. Fischer ,  Erez Carmel ,  Thomas F. Heil

    发明人： Stephen A. Fischer ,  Erez Carmel ,  Thomas F. Heil

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/16

    CPC分类号： G06F13/1689 ,  G06F12/0215

    摘要： A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control interface state tracker is then connected to the memory controller. A separate clock independent from the one used with the CPU is coupled to the memory controller and drives the operation of the memory controller. During the operation of the computer system, the CPU makes read or write cycle requests of the memory controller. Such cycles are initiated when the CPU sends a cycle "start" indicator to the state tracker. In response, the state tracker activates a start strobe to the memory controller to start the actual memory cycle. The memory controller receives the CPU address and cycle status and determines the page hit/miss condition of the memory access. Using this information, the appropriate register in the cycle length register file is accessed to obtain a cycle length feedback value indicating the quantity of wait states necessary for the particular memory cycle. This cycle length feedback value is sent to the external control interface state tracker. The state tracker then returns a ready indication to the CPU after the cycle length time has been satisfied as indicated by the cycle length feedback.

    摘要翻译： 存储器控制器与高速同步CPU接口的方法和方法，其中CPU时钟独立于存储器控制器时钟。 CPU时钟连接到位于存储器控制器外部的CPU和控制接口状态跟踪器。 然后，控制接口状态跟踪器连接到存储器控制器。 独立于与CPU一起使用的时钟的单独时钟耦合到存储器控制器并驱动存储器控制器的操作。 在计算机系统的操作期间，CPU对存储器控制器进行读或写周期请求。 当CPU向状态跟踪器发送周期“开始”指示符时，启动这种周期。 作为响应，状态跟踪器激活对存储器控制器的启动选通以开始实际的存储器周期。 存储器控制器接收CPU地址和周期状态，并确定存储器访问的页命中/未命中状态。 使用该信息，访问循环长度寄存器文件中的适当寄存器以获得指示特定存储器周期所需的等待状态量的周期长度反馈值。 该周期长度反馈值被发送到外部控制接口状态跟踪器。 状态跟踪器然后在周期长度反馈已经满足循环长度时间之后，向CPU返回就绪指示。

    System and method for limiting exposure of hardware failure information for a secured execution environment
    60.
    发明授权
    System and method for limiting exposure of hardware failure information for a secured execution environment 有权
    用于限制安全执行环境的硬件故障信息暴露的系统和方法

    公开(公告)号：US07934076B2

    公开(公告)日：2011-04-26

    申请号：US10956322

    申请日：2004-09-30

    申请人： Stephen A. Fischer ,  Shamanna M. Datta

    发明人： Stephen A. Fischer ,  Shamanna M. Datta

    IPC分类号： G06F9/00

    CPC分类号： G06F21/74 ,  G06F2221/2101

    摘要： A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.

    摘要翻译： 描述了用于限制硬件故障信息的暴露的方法和装置。 在一个实施例中，处理器的错误报告系统可以将各种状态和错误地址数据记录到通过热复位事件保留其内容的寄存器中。 但是处理器的错误报告系统然后可以确定处理器是否以可信任或安全模式操作。 如果没有，则处理器的体系结构状态变量也可能被记录到寄存器中。 但是，如果处理器以可信任或安全模式运行，则可能会禁止对架构状态变量的日志记录或标记为无效。