公开(公告)号：US20160133638A1

公开(公告)日：2016-05-12

申请号：US14536021

申请日：2014-11-07

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/8221 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Abstract translation: 一些实施例包括具有源材料，源材料上方的介电材料，介电材料上方的选择栅极材料，选择栅极材料上方的存储单元堆叠，位于介电材料的开口中的导电插塞的装置和方法，以及 接触源材料的一部分，以及延伸穿过存储单元堆叠和选择栅极材料并与导电插塞接触的沟道材料。

公开(公告)号：US20160099252A1

公开(公告)日：2016-04-07

申请号：US14831011

申请日：2015-08-20

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/11582 ,  H01L29/7827

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

Abstract translation: 本公开包括具有连续信道的存储器及其处理方法。 许多实施例包括形成具有串联连接在源选择栅极和漏极选择栅极之间的存储单元的垂直堆叠，其中形成垂直堆叠包括形成用于源选择栅极，存储器单元和漏极选择的连续沟道 栅极，并且去除用于漏极选择栅极的连续沟道的一部分，使得连续沟道对于漏极选择栅极比对于存储器单元和源选择栅极更薄。

公开(公告)号：US20150333143A1

公开(公告)日：2015-11-19

申请号：US14281569

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

公开(公告)号：US20150004786A1

公开(公告)日：2015-01-01

申请号：US14486890

申请日：2014-09-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luan C. Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract translation: 用于限定集成电路中的图案的方法包括在衬底的第一区域上使用光刻法在第一光致抗蚀剂层中限定多个特征。 该方法还包括使用音调倍增以在光致抗蚀剂层中的每个特征的下掩蔽层中产生至少两个特征。 下掩蔽层中的特征包括环形端。 该方法还包括用第二光致抗蚀剂层覆盖包括下掩蔽层中的环状末端的衬底的第二区域。 该方法还包括通过下掩蔽层中的特征蚀刻衬底中的沟槽图案，而不在第二区域内进行蚀刻。 沟槽具有沟槽宽度。

公开(公告)号：US20130210228A1

公开(公告)日：2013-08-15

申请号：US13852275

申请日：2013-03-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luan C. Tran

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/11521

Abstract: Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.

Abstract translation: 公开了形成用于集成电路的导电和/或半导体特征的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。 常规的光刻步骤可以与俯仰减小技术组合使用以形成例如细长的俯仰特征，例如位线接触。

公开(公告)号：US12274056B2

公开(公告)日：2025-04-08

申请号：US18433863

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H10B41/27 ,  G11C5/06 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US11380699B2

公开(公告)日：2022-07-05

申请号：US16288982

申请日：2019-02-28

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H01L27/11556 ,  H01L27/1157 ,  G11C5/06 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11582

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US11348788B2

公开(公告)日：2022-05-31

申请号：US16692440

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Raghupathy Giridhar

IPC: H01L21/027 ,  H01L27/105 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/311

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

公开(公告)号：US11315941B2

公开(公告)日：2022-04-26

申请号：US16291453

申请日：2019-03-04

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

IPC: H01L27/11556 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/11582 ,  H01L29/78

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

公开(公告)号：US11011531B2

公开(公告)日：2021-05-18

申请号：US15555046

申请日：2016-03-16

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran

IPC: H01L27/11556 ,  H01L21/02 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

Abstract: Disclosed are memory structures and methods for forming such structures. An example method forms a vertical string of memory cells by forming an opening in interleaved tiers of dielectric tier material and nitride tier material, forming a charge storage material over sidewalls of the opening and recesses in the opening to form respective charge storage structures within the recesses. Subsequently, and separate from the formation of the floating gate structures, at least a portion of the remaining nitride tier material is removed to produce control gate recesses, each adjacent a respective charge storage structure. A control gate is formed in each control gate recess, and the control gate is separated from the charge storage structure by a dielectric structure. In some examples, these dielectric structures are also formed separately from the charge storage structures.