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公开(公告)号：US20140254258A1
公开(公告)日：2014-09-11
申请号：US14287946
申请日：2014-05-27
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Mingdong Cui
CPC classification number: G11C13/004 , G05F1/461 , G05F3/16 , G11C5/147 , G11C7/062 , G11C7/14 , G11C8/08 , G11C13/0004 , G11C13/0038 , G11C2013/0054
Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
Abstract translation: 所描述的示例包括用于向感测电路提供参考电压的感测电路和参考电压发生器。 感测电路可以感测可以是PCM存储器单元的存储器单元的状态。 感测电路可以包括共源共栅晶体管。 参考电压发生器的示例可以包括耦合到多个组参考电压发生器的全局参考电压发生器，其可以减小电压发生器路由的输出电阻。
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公开(公告)号：US20250118341A1
公开(公告)日：2025-04-10
申请号：US18919142
申请日：2024-10-17
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Mingdong Cui , Richard E. Fackenthal
Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
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公开(公告)号：US12176020B2
公开(公告)日：2024-12-24
申请号：US17821645
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Mingdong Cui , Richard E. Fackenthal
IPC: G11C8/14 , G11C5/02 , G11C11/22 , G11C11/408 , G11C11/4091 , G11C5/06 , G11C11/401
Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
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公开(公告)号：US12131794B2
公开(公告)日：2024-10-29
申请号：US17893681
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Mingdong Cui , Richard E. Fackenthal
CPC classification number: G11C5/025 , G11C5/063 , G11C8/14 , H10B12/488
Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
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公开(公告)号：US20240265965A1
公开(公告)日：2024-08-08
申请号：US18639690
申请日：2024-04-18
Applicant: Micron Technology, Inc.
Inventor： Vijayakrishna J. Vankayala , Hari Giduturi , Jeffrey E. Koelling , Mingdong Cui , Ramachandra Rao Jogu
CPC classification number: G11C13/0023 , G11C13/0004 , G11C2213/15 , H03K19/20
Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.
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Patent Agency Ranking
公开(公告)号：US12057178B2
公开(公告)日：2024-08-06
申请号：US17831266
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Inventor： Kijun Nam , Mingdong Cui
CPC classification number: G11C16/30 , G11C5/14 , G11C16/12 , G11C16/26 , G11C16/3418
Abstract: In some aspects, the techniques described herein relate to a circuit including: a memory cell; a source follower, a source terminal of the source follower communicatively coupled to the memory cell; a voltage source; an operational amplifier, a non-inverting input of the operational amplifier communicatively coupled to the voltage source; and a replica source follower, a gate of the replica source follower communicatively coupled to an output of the operational amplifier and a source terminal of the replica source follower communicatively coupled to an inverting input of the operational amplifier via a feedback loop.
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公开(公告)号：US11990176B2
公开(公告)日：2024-05-21
申请号：US17831332
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Inventor： Jin Seung Son , Mingdong Cui
IPC: G11C13/00 , G11C11/4074 , G11C11/408 , G11C11/4093 , G11C11/4096
CPC classification number: G11C11/4087 , G11C11/4074 , G11C11/4093 , G11C11/4096
Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.
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公开(公告)号：US20240071467A1
公开(公告)日：2024-02-29
申请号：US17893654
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Mingdong Cui
IPC: G11C11/408 , H10B80/00
CPC classification number: G11C11/4085 , G11C11/4087 , H10B80/00
Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.
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公开(公告)号：US11587635B2
公开(公告)日：2023-02-21
申请号：US17013089
申请日：2020-09-04
Applicant: Micron Technology, Inc.
Inventor： Hongmei Wang , Nevil N. Gajera , Mingdong Cui , Fabio Pellizzer
Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.
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公开(公告)号：US11527286B2
公开(公告)日：2022-12-13
申请号：US17375441
申请日：2021-07-14
Applicant: Micron Technology, Inc.
Inventor： Mingdong Cui , Nathan Joseph Sirocka , Hari Giduturi
Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.
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