公开(公告)号：US11937429B2

公开(公告)日：2024-03-19

申请号：US17556704

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/1157 ,  H01L23/528 ,  H01L23/532 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/528 ,  H01L23/53257 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：USRE49715E1

公开(公告)日：2023-10-24

申请号：US17463420

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Martin C. Roberts ,  Sanh D. Tang ,  Fred D. Fishburn

IPC: H01L29/08 ,  H10B12/00 ,  H10B53/20 ,  H01L23/528 ,  H10B53/10 ,  H01L29/10 ,  H10B53/30 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/06 ,  H01L21/306 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L29/0847 ,  H01L23/528 ,  H01L28/60 ,  H01L29/1033 ,  H01L29/42376 ,  H10B12/03 ,  H10B12/05 ,  H10B12/30 ,  H10B12/48 ,  H10B12/50 ,  H10B53/10 ,  H10B53/20 ,  H10B53/30 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32134 ,  H01L27/0688

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

公开(公告)号：US11239252B2

公开(公告)日：2022-02-01

申请号：US16907967

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US10825815B2

公开(公告)日：2020-11-03

申请号：US15973707

申请日：2018-05-08

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Martin C. Roberts

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11507 ,  H01L49/02 ,  H01L27/06 ,  H01L29/78 ,  H01L21/265 ,  H01L27/11514 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/306 ,  H01L27/11597

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.

公开(公告)号：US10720446B2

公开(公告)日：2020-07-21

申请号：US16158039

申请日：2018-10-11

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US10607995B2

公开(公告)日：2020-03-31

申请号：US15973697

申请日：2018-05-08

Applicant: Micron Technology, Inc.

Inventor： Martin C. Roberts ,  Sanh D. Tang ,  Fred D. Fishburn

IPC: H01L27/108 ,  H01L29/08 ,  H01L29/10 ,  H01L49/02 ,  H01L23/528 ,  H01L29/423 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514 ,  H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/06

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

公开(公告)号：US20190229127A1

公开(公告)日：2019-07-25

申请号：US16372563

申请日：2019-04-02

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US10256249B2

公开(公告)日：2019-04-09

申请号：US15651719

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20190103406A1

公开(公告)日：2019-04-04

申请号：US16192462

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Martin C. Roberts ,  Gurtej S. Sandhu

IPC: H01L27/108 ,  H01L29/786

Abstract: Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

公开(公告)号：US10242726B1

公开(公告)日：2019-03-26

申请号：US16180542

申请日：2018-11-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.