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177 条记录 (耗时 0.035 秒)

    Method of forming semiconductor devices with differently composed metal-based gate electrodes
    52.
    发明授权
    Method of forming semiconductor devices with differently composed metal-based gate electrodes 有权
    用不同组合的金属基栅极形成半导体器件的方法

    公开(公告)号：US06518154B1

    公开(公告)日：2003-02-11

    申请号：US09813310

    申请日：2001-03-21

    申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

    发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

    IPC分类号： H01L213205

    CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

    摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.

    摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如， ，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。 本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

    Test structure for providing depth of polish feedback
    53.
    发明授权
    Test structure for providing depth of polish feedback 失效
    提供抛光反馈深度的测试结构

    公开(公告)号：US06514858B1

    公开(公告)日：2003-02-04

    申请号：US09829202

    申请日：2001-04-09

    申请人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    发明人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    IPC分类号： H01L214763

    CPC分类号： H01L22/34 ,  B24B37/042 ,  B24B49/00 ,  H01L21/31053 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

    摘要翻译： 提供了一种用于控制半导体器件的抛光工艺的测试结构。 测试结构由结构层，第一处理层和互连构成。 第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。 多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。 开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。 因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

    Metal gate stack with etch stop layer having implanted metal species
    54.
    发明授权
    Metal gate stack with etch stop layer having implanted metal species 有权
    具有蚀刻停止层的具有植入金属物质的金属栅极叠层

    公开(公告)号：US06444513B1

    公开(公告)日：2002-09-03

    申请号：US09810348

    申请日：2001-03-19

    申请人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

    发明人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L218238

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  Y10S438/947 ,  Y10S438/949

    摘要： A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

    摘要翻译： 金属栅结构及其形成方法将金属杂质引入例如由TiN制成的第一金属层中。 这些杂质产生更大的蚀刻选择性的表面区域，其防止了在形成金属栅极结构期间在覆盖钨栅的蚀刻过程中TiN的过蚀刻。 防止TiN的过蚀刻保护栅极氧化物免受不希望的退化。 提供铝或钽作为金属杂质提供了足够的蚀刻停止能力，并且不会不希望地影响TiN的功函数。

    Silicide gate transistors
    56.
    发明授权
    Silicide gate transistors 有权
    硅化物栅极晶体管

    公开(公告)号：US06368950B1

    公开(公告)日：2002-04-09

    申请号：US09734186

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L213205

    CPC分类号： H01L29/66545 ,  H01L21/28097

    摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

    摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

    Method of forming cobalt silicide
    58.
    发明授权
    Method of forming cobalt silicide 有权
    形成硅化钴的方法

    公开(公告)号：US06329277B1

    公开(公告)日：2001-12-11

    申请号：US09417839

    申请日：1999-10-14

    申请人： Bill Yowjuang Liu ,  Paul R. Besser

    发明人： Bill Yowjuang Liu ,  Paul R. Besser

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： A semiconductor arrangement and method of forming silicide regions includes conformally depositing a reducing material layer on a silicon substrate. A refractory metal layer is then conformally deposited on the reducing material layer. Annealing is then performed to form a refractory metal silicide layer on the silicon substrate. The metal silicide layer is a cobalt silicide and the reducing material layer includes at least one of tantalum, magnesium, aluminum or calcium. The reducing material reduces native oxide on a silicon substrate to allow the cobalt silicide to form.

    摘要翻译： 形成硅化物区域的半导体布置和方法包括在硅衬底上共形沉积还原材料层。 然后将难熔金属层共形沉积在还原材料层上。 然后进行退火以在硅衬底上形成难熔金属硅化物层。 金属硅化物层是硅化钴，还原材料层包括钽，镁，铝或钙中的至少一种。 还原材料减少硅衬底上的自然氧化物以形成硅化钴。