Abstract:
A substrate that includes at least one dielectric layer, a plurality of first interconnects located in the at least one dielectric layer, at least one photo-imageable dielectric layer coupled to the at least one dielectric layer, and a plurality of second interconnects located in the at least one photo-imageable dielectric layer. The plurality of second interconnects includes at least one pair of adjacent interconnects having a centroid to centroid distance that is less than a pitch between the pair of interconnects. The pair of adjacent interconnects may include a pair of adjacent via interconnects and/or a pair of pad interconnects. The substrate may include a coreless substrate or a cored substrate.
Abstract:
Disclosed is an apparatus and methods for making same. The apparatus includes a substrate, a set of electrical contacts disposed on the surface of the substrate, and an electromagnetic interference (EMI) shield pedestal structure, disposed between an outer periphery of the set of electrical contacts and an outer portion of the substrate.
Abstract:
Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.
Abstract:
A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
Abstract:
Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.
Abstract:
An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.
Abstract:
Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.
Abstract:
A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.
Abstract:
Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.
Abstract:
Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.