HYBRID PACKAGE APPARATUS AND METHOD OF FABRICATING

    公开(公告)号:US20210305141A1

    公开(公告)日:2021-09-30

    申请号:US17211164

    申请日:2021-03-24

    Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

    Integrated circuit package comprising surface capacitor and ground plane

    公开(公告)号:US10181410B2

    公开(公告)日:2019-01-15

    申请号:US14634547

    申请日:2015-02-27

    Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

    Integrated device comprising via with side barrier layer traversing encapsulation layer
    57.
    发明授权
    Integrated device comprising via with side barrier layer traversing encapsulation layer 有权
    集成装置,其包括通过侧向阻挡层穿过封装层的通孔

    公开(公告)号:US09466554B2

    公开(公告)日:2016-10-11

    申请号:US14274517

    申请日:2014-05-09

    Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

    Abstract translation: 一些新颖的特征涉及包括封装层,穿过封装层的通孔结构和衬垫的集成器件。 通孔结构包括通孔,其包括第一侧,第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中,集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中,集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中,集成器件包括耦合到衬底的第一管芯,其中封装层封装第一管芯。 在一些实施方式中,通孔包括被配置为作为垫进行操作的部分。

    Integrated device comprising high density interconnects and redistribution layers
    60.
    发明授权
    Integrated device comprising high density interconnects and redistribution layers 有权
    集成器件包括高密度互连和再分配层

    公开(公告)号:US09230936B2

    公开(公告)日:2016-01-05

    申请号:US14196817

    申请日:2014-03-04

    Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

    Abstract translation: 一些新颖的特征涉及一种集成器件(例如,集成封装),其包括用于集成器件的基座部分,耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中,集成器件还包括封装第一裸片的封装材料。 在一些实施方案中,集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中,集成器件还包括在基部上的一组互连,该组互连电耦合第一管芯和第二管芯。 在一些实施方案中,第一管芯包括第一组互连柱,并且第二管芯包括第二组互连柱。

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