公开(公告)号：US11296022B2

公开(公告)日：2022-04-05

申请号：US17002615

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/528 ,  H01L21/768

Abstract: A substrate that includes at least one dielectric layer, a plurality of first interconnects located in the at least one dielectric layer, at least one photo-imageable dielectric layer coupled to the at least one dielectric layer, and a plurality of second interconnects located in the at least one photo-imageable dielectric layer. The plurality of second interconnects includes at least one pair of adjacent interconnects having a centroid to centroid distance that is less than a pitch between the pair of interconnects. The pair of adjacent interconnects may include a pair of adjacent via interconnects and/or a pair of pad interconnects. The substrate may include a coreless substrate or a cored substrate.

公开(公告)号：US11177223B1

公开(公告)日：2021-11-16

申请号：US17010676

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Brigham Navaja

IPC: H05K1/02 ,  H01L23/552 ,  H05K1/09 ,  H05K1/11

Abstract: Disclosed is an apparatus and methods for making same. The apparatus includes a substrate, a set of electrical contacts disposed on the surface of the substrate, and an electromagnetic interference (EMI) shield pedestal structure, disposed between an outer periphery of the set of electrical contacts and an outer portion of the substrate.

公开(公告)号：US20210305141A1

公开(公告)日：2021-09-30

申请号：US17211164

申请日：2021-03-24

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Brigham Navaja

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48

Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

公开(公告)号：US10410971B2

公开(公告)日：2019-09-10

申请号：US15689967

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： David Fraser Rae ,  Hong Bok We ,  Christopher Healy ,  Chin-Kwan Kim

IPC: H01L23/13 ,  H01L23/552 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/373 ,  H01L23/498 ,  H01L23/367

Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.

公开(公告)号：US10181410B2

公开(公告)日：2019-01-15

申请号：US14634547

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01G4/12 ,  H01G4/224 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

公开(公告)号：US09583433B2

公开(公告)日：2017-02-28

申请号：US14631391

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01L29/66 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L49/02 ,  H01F27/28 ,  H01F27/29 ,  H01L23/64 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/063 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Abstract translation: 集成器件封装包括封装衬底，耦合到封装衬底的管芯，封装管芯的封装层以及配置成作为电感器工作的至少一片导电材料。 导电材料片材至少部分地被封装层封装。 导电材料片被配置为作为螺线管电感器工作。 导电材料片包括第一片部分，第二片部分，其耦合到第一片部分，第一片部分和第二片部分形成电感器的第一绕组，第一端部分耦合到第一片 部分，以及耦合到第二片部分的第二端子部分。 第一片部分形成在片材的第一层上。 第二片部分形成在片材的第二层上。

公开(公告)号：US09466554B2

公开(公告)日：2016-10-11

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L21/4763 ,  H01L23/48 ,  H01L23/50 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和衬垫的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US09401350B1

公开(公告)日：2016-07-26

申请号：US14812476

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L25/18 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L21/52 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

Abstract translation: 公开了一种封装封装（POP）结构。 POP结构包括第一裸片，第二裸片和光成像电介质（PID）层。 PID层设置在第一管芯和第二管芯之间。 POP结构还包括从第一管芯通过PID层到第二管芯的第一导电路径。 第一导电路径直接在第一管芯和第二管芯之间直接延伸通过PID层的第一区域。 POP结构还包括从第一管芯通过PID层到第二管芯的第二导电路径。 第二导电路径的特定部分垂直于第一导电路径并且不直接在第一管芯和第二管芯之间延伸穿过PID层的第二区域。

公开(公告)号：US20160133571A1

公开(公告)日：2016-05-12

申请号：US14535966

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。

公开(公告)号：US09230936B2

公开(公告)日：2016-01-05

申请号：US14196817

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

Abstract translation: 一些新颖的特征涉及一种集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电耦合第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。