公开(公告)号：US10181410B2

公开(公告)日：2019-01-15

申请号：US14634547

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01G4/12 ,  H01G4/224 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

公开(公告)号：US09933455B2

公开(公告)日：2018-04-03

申请号：US14703677

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  G01R29/08 ,  G01R1/067

CPC classification number: G01R1/045 ,  G01R1/06722 ,  G01R1/06772 ,  G01R1/07314 ,  G01R29/08 ,  G01R31/2822

Abstract: Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

公开(公告)号：US09807884B2

公开(公告)日：2017-10-31

申请号：US14579651

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H05K3/40 ,  H01G4/248 ,  H01G4/012 ,  H01G4/005 ,  H01G4/232 ,  H01L23/538 ,  H01L23/50 ,  H01G4/30 ,  H01L23/00 ,  H01L25/065

CPC classification number: H05K1/185 ,  H01G4/005 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.

公开(公告)号：US09583433B2

公开(公告)日：2017-02-28

申请号：US14631391

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H01L29/66 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L49/02 ,  H01F27/28 ,  H01F27/29 ,  H01L23/64 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/063 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

Abstract translation: 集成器件封装包括封装衬底，耦合到封装衬底的管芯，封装管芯的封装层以及配置成作为电感器工作的至少一片导电材料。 导电材料片材至少部分地被封装层封装。 导电材料片被配置为作为螺线管电感器工作。 导电材料片包括第一片部分，第二片部分，其耦合到第一片部分，第一片部分和第二片部分形成电感器的第一绕组，第一端部分耦合到第一片 部分，以及耦合到第二片部分的第二端子部分。 第一片部分形成在片材的第一层上。 第二片部分形成在片材的第二层上。

公开(公告)号：US09530739B2

公开(公告)日：2016-12-27

申请号：US14609289

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/552 ,  H01L23/60 ,  H01L25/10

CPC classification number: H01L23/5384 ,  H01L21/768 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1047 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the first package substrate, an encapsulation layer located on the first package substrate, and an inter package connection coupled to the first package substrate. The inter package connection is located in the encapsulation layer. The inter package connection includes a first interconnect configured to provide a first electrical path for a reference ground signal, and a second set of interconnects configured to provide at least one second electrical path for at least one second signal. The first interconnect has a length that is at least about twice as long as a width of the first interconnect. The second set of interconnects is configured to at least be partially coupled to the first interconnect by an electric field.

Abstract translation: 包装（PoP）装置包括第一包装和第二包装。 第一封装包括第一封装衬底，耦合到第一封装衬底的管芯，位于第一封装衬底上的封装层以及耦合到第一封装衬底的封装间连接。 封装间连接位于封装层中。 所述间隔间连接包括被配置为提供用于参考接地信号的第一电路径的第一互连和被配置为为至少一个第二信号提供至少一个第二电路径的第二组互连。 第一互连的长度至少是第一互连宽度的两倍。 第二组互连被配置为通过电场至少部分地耦合到第一互连。

公开(公告)号：US20150325375A1

公开(公告)日：2015-11-12

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01G4/30 ,  H05K3/46 ,  H05K1/11 ,  H01G2/02 ,  H05K1/18

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20150294791A1

公开(公告)日：2015-10-15

申请号：US14252695

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Hong Bok We ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01G4/30 ,  H05K1/18 ,  H01G4/005 ,  H05K1/02 ,  H01L23/00 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/232 ,  H01G4/33 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/32265 ,  H01L2224/83801 ,  H01L2924/1205 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: A ceramic capacitor is provided that includes a first capacitor surface, a second opposing capacitor surface, and metal plates perpendicular to the first capacitor surface and second opposing capacitor surface. The metal plates extend from the first capacitor surface to the second opposing capacitor surface. The ceramic capacitor is capable of being interposed between a die and a substrate. A portion of the metal plates are capable of being coupled to conductive pads of the die on the first capacitor surface and to conductive pads of the substrate on the second capacitor surface.

Abstract translation: 提供一种陶瓷电容器，其包括第一电容器表面，第二相对电容器表面和垂直于第一电容器表面和第二相对电容器表面的金属板。 金属板从第一电容器表面延伸到第二相对的电容器表面。 陶瓷电容器能够插入在管芯和衬底之间。 金属板的一部分能够耦合到第一电容器表面上的管芯的导电焊盘和第二电容器表面上的衬底的导电焊盘。

公开(公告)号：US20150130024A1

公开(公告)日：2015-05-14

申请号：US14079503

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L27/08 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/306 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L27/0805 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16267 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/014

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract translation: 提供了一种层叠电容器，其包括多个通孔，其构造成从模具接收互连。

公开(公告)号：US09659850B2

公开(公告)日：2017-05-23

申请号：US14563854

申请日：2014-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H01L23/66 ,  H01L23/482 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/162 ,  H01L2924/00

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

公开(公告)号：US09628052B2

公开(公告)日：2017-04-18

申请号：US14249189

申请日：2014-04-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/50 ,  H03K3/013 ,  H05K1/18 ,  H05K1/03 ,  H05K3/46 ,  G05F3/08 ,  H05K3/30 ,  H01L23/498 ,  H01L23/00

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.