公开(公告)号：US10079293B2

公开(公告)日：2018-09-18

申请号：US15839050

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US20180076197A1

公开(公告)日：2018-03-15

申请号：US15266214

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Haining Yang ,  Jun Yuan ,  Kern Rim ,  Periannan Chidambaram

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/785

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.

公开(公告)号：US20180006035A1

公开(公告)日：2018-01-04

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/28035 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/7846

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US20170278842A1

公开(公告)日：2017-09-28

申请号：US15081702

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

公开(公告)号：US20170170268A1

公开(公告)日：2017-06-15

申请号：US15367320

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Peijie Feng ,  Kern Rim ,  Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L21/324 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/78696

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures. The gate material extends in the separation areas between adjacent nanowire structures sufficient to create a fringing field to the channel where gate material is not adjacently disposed, to provide strong gate control of the channel even though gate material does not completely surround the rounded nanowire structures.

公开(公告)号：US09660649B2

公开(公告)日：2017-05-23

申请号：US14639755

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H03L5/00 ,  H03K19/00 ,  H03K19/0185 ,  G06F1/32 ,  G06F17/50

CPC classification number: H03K19/0016 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3296 ,  G06F17/505 ,  G06F2209/5019 ,  G06F2217/68 ,  G06F2217/78 ,  H03K19/018507 ,  Y02D10/172 ,  Y02D10/174

Abstract: A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication.

公开(公告)号：US09542518B2

公开(公告)日：2017-01-10

申请号：US14656426

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: G06F17/50 ,  G06F15/76

CPC classification number: G06F17/5045 ,  G06F15/76

Abstract: A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are determined based on the first usage conditions and the second usage conditions.

Abstract translation: 一种用于设计用于无线设备的片上系统（SOC）的方法包括：在设计处理器处接收所述SOC的第一模块的第一使用条件和所述SOC的第二模块的第二使用条件。 该方法还包括确定SOC的设计参数。 基于第一使用条件和第二使用条件来确定设计参数。

公开(公告)号：US09379058B2

公开(公告)日：2016-06-28

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Ohsang Kwon ,  Kern Rim ,  John Jianhong Zhu ,  Xiangdong Chen ,  Foua Vang ,  Raymond George Stephany ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20160163714A1

公开(公告)日：2016-06-09

申请号：US14559258

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

Abstract translation: 公开了在SRAM位单元的边界边缘分割的具有字线着色焊盘的静态随机存取存储器（SRAM）位单元。 一方面，公开了在第二金属层中采用写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线具有更宽的宽度，这降低了字线电阻，减少了访问时间，并且提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨道。 为了将读取字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在SRAM位单元的边界内部和外部的对应轨道上。 对应于写入字线的着陆焊盘被放置在SRAM位单元的边界边缘内的对应的轨道上。

公开(公告)号：US20160140275A1

公开(公告)日：2016-05-19

申请号：US14656426

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F15/76

Abstract: A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are based on the first usage conditions and the second usage conditions.

Abstract translation: 一种用于设计用于无线设备的片上系统（SOC）的方法包括：在设计处理器处接收所述SOC的第一模块的第一使用条件和所述SOC的第二模块的第二使用条件。 该方法还包括确定SOC的设计参数。 设计参数基于第一使用条件和第二使用条件。