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    Data Transmission Using Delayed Timing Signals
    51.
    发明申请
    Data Transmission Using Delayed Timing Signals 有权

    公开(公告)号：US20230073567A1

    公开(公告)日：2023-03-09

    申请号：US17883345

    申请日：2022-08-08

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Memory System Topologies Including A Memory Die Stack
    52.
    发明申请
    Memory System Topologies Including A Memory Die Stack 有权

    公开(公告)号：US20220336008A1

    公开(公告)日：2022-10-20

    申请号：US17717632

    申请日：2022-04-11

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C11/4093 ,  G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/065 ,  H01L25/10

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
    53.
    发明申请
    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT 有权

    公开(公告)号：US20220221989A1

    公开(公告)日：2022-07-14

    申请号：US17586575

    申请日：2022-01-27

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    Memory system with threaded transaction support
    54.
    发明授权
    Memory system with threaded transaction support 有权

    公开(公告)号：US11249649B2

    公开(公告)日：2022-02-15

    申请号：US16805535

    申请日：2020-02-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING
    55.
    发明申请
    MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING 审中-公开

    公开(公告)号：US20200371868A1

    公开(公告)日：2020-11-26

    申请号：US16872929

    申请日：2020-05-12

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F11/10 ,  G06F11/16 ,  G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/52 ,  G11C29/00 ,  H03M13/15

    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

    DRAM retention monitoring method for dynamic error correction
    59.
    发明授权
    DRAM retention monitoring method for dynamic error correction 有权
    用于动态纠错的DRAM保留监控方法

    公开(公告)号：US09411678B1

    公开(公告)日：2016-08-09

    申请号：US13828828

    申请日：2013-03-14

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ely Tsern ,  Thomas Vogelsang ,  Wayne Ellis

    IPC: H03M13/00 ,  G06F11/10

    CPC classification number: G06F11/1008

    Abstract: A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.

    Abstract translation: 一种在存储器件中的操作方法，包括将数据存储在存储器件中的第一组存储位置中，将与存储的数据相关联的错误信息存储在存储器件中的第二组存储位置中，并且选择性地评估误差信息 基于错误使能位的状态，基于对第一组存储位置的最近访问是否涉及部分访问的状态。

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