公开(公告)号：US20180246783A1

公开(公告)日：2018-08-30

申请号：US15968468

申请日：2018-05-01

Applicant: SanDisk Technologies LLC

Inventor： David Avraham ,  Ran Zamir ,  Eran Sharon

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/17 ,  G06F17/30

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

公开(公告)号：US09959168B2

公开(公告)日：2018-05-01

申请号：US15177822

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Stella Achtenberg ,  Eran Sharon ,  Idan Alrod

IPC: H03M13/27 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  H03M13/15

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0644 ,  G06F11/1012 ,  G06F11/108 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/3707

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.

公开(公告)号：US20180113759A1

公开(公告)日：2018-04-26

申请号：US15333440

申请日：2016-10-25

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/52 ,  G11C2207/2281

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US09940194B2

公开(公告)日：2018-04-10

申请号：US15177887

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Stella Achtenberg ,  Eran Sharon ,  Idan Alrod

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/11

CPC classification number: G06F3/0689 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0644 ,  G06F11/1012 ,  G06F11/108 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2957 ,  H03M13/6325

Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.

公开(公告)号：US09792174B2

公开(公告)日：2017-10-17

申请号：US14841317

申请日：2015-08-31

Applicant: SanDisk Technologies LLC

Inventor： Damian Pablo Yurzola ,  Eran Sharon ,  Idan Alrod ,  Michael Altshuler ,  Madhuri Kotagiri ,  Rajeev Nagabhirava

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

公开(公告)号：US20170228299A1

公开(公告)日：2017-08-10

申请号：US15414442

申请日：2017-01-24

Applicant: SanDisk Technologies LLC

Inventor： Ofer Shapira ,  Idan Alrod ,  Eran Sharon

IPC: G06F11/20 ,  G11C11/56 ,  G06F3/06 ,  G11C16/04

CPC classification number: G06F11/2094 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0665 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/073 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/025 ,  G11C29/52

Abstract: Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.