公开(公告)号：US10325812B2

公开(公告)日：2019-06-18

申请号：US15950291

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L21/283 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L27/088 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12

Abstract: A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

公开(公告)号：US10056453B2

公开(公告)日：2018-08-21

申请号：US15217643

申请日：2016-07-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Srinivasa R. Banna ,  Deepak K. Nayak ,  Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L23/00 ,  H01L29/20 ,  H01L29/16 ,  H01L29/267 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/562 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

公开(公告)号：US09960257B2

公开(公告)日：2018-05-01

申请号：US14656671

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545

Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

公开(公告)号：US09748387B2

公开(公告)日：2017-08-29

申请号：US14940655

申请日：2015-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/7781

Abstract: One method disclosed includes forming first, second and third fins for a first NMOS device, a PMOS device and a second NMOS device, respectively. According to this method, the first fin consists entirely of the substrate material, the second and third fins comprise a lower substrate fin portion made of the substrate material and an upper fin portion made of a second semiconductor material and a third semiconductor material, respectively, wherein the second semiconductor material and the third semiconductor material are each different from the substrate material. The method also includes forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device.

公开(公告)号：US09673083B2

公开(公告)日：2017-06-06

申请号：US14608729

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/76213 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

公开(公告)号：US09484428B2

公开(公告)日：2016-11-01

申请号：US14608288

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L29/0649 ,  H01L29/401

Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.

Abstract translation: 半导体器件包括限定在基极层上的第一栅电极。 第一多个层设置在第一栅电极的第一侧壁上。 第一多个层包括形成在第一侧壁上的第一介电层，形成在第一介电层上的第一弹道导体层，形成在第一弹道导体层上的中间层，形成在中间层上的第二弹道导体层， 以及形成在所述第二弹道导体层上方的第二电介质层。 第二栅电极接触第二电介质层。

公开(公告)号：US20160254195A1

公开(公告)日：2016-09-01

申请号：US14633353

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/161 ,  H01L29/16 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract translation: 本文公开的一种说明性方法包括形成多个初始翅片，其具有与基底相同的初始轴向长度和相同的初始应变，执行至少一个蚀刻工艺以将第一翅片切割成第一轴向 并且将第二翅片切割成小于第一轴向长度的第二轴向长度，其中切割的第一翅片保持初始应变的第一量，并且切割的第二翅片保持初始应变的约零或第二量 的初始应变小于第一量，并且围绕第一和第二切割翅片形成栅极结构以形成FinFET器件。

公开(公告)号：US20160225870A1

公开(公告)日：2016-08-04

申请号：US14608288

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L29/0649 ,  H01L29/401

Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.

Abstract translation: 半导体器件包括限定在基极层上的第一栅电极。 第一多个层设置在第一栅电极的第一侧壁上。 第一多个层包括形成在第一侧壁上的第一介电层，形成在第一介电层上的第一弹道导体层，形成在第一弹道导体层上的中间层，形成在中间层上的第二弹道导体层， 以及形成在所述第二弹道导体层上方的第二电介质层。 第二栅电极接触第二电介质层。

公开(公告)号：US20160225719A1

公开(公告)日：2016-08-04

申请号：US14608337

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L23/532 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2221/1094

Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.

Abstract translation: 一种方法包括在第一电介质层中形成折叠模板。 折叠模板具有位于不同平面中的多个表面。 弹性导线形成在折叠模板的多个表面上。 一种器件包括设置在第一介电层中的第一介质层和垂直折叠线，垂直折叠线包括弹道导体材料。

公开(公告)号：US20160225677A1

公开(公告)日：2016-08-04

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/84 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域