公开(公告)号：US20180247874A1

公开(公告)日：2018-08-30

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01C7/12 ,  H01L27/08 ,  H01L49/02 ,  H01L21/74

CPC classification number: H01L21/823493 ,  H01C7/126 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/765 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/8605

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US10002906B2

公开(公告)日：2018-06-19

申请号：US15365143

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/36 ,  H01L27/24 ,  H01L27/12 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/1203 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US09941012B2

公开(公告)日：2018-04-10

申请号：US15453663

申请日：2017-03-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L29/66 ,  G11C16/26 ,  G11C7/18 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  G11C16/08 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423 ,  H01L27/02

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

公开(公告)号：US20170352703A1

公开(公告)日：2017-12-07

申请号：US15365143

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/24 ,  H01L27/12 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/1203 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US09653470B2

公开(公告)日：2017-05-16

申请号：US14671606

申请日：2015-03-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L21/28 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  G11C16/14 ,  H01L29/66 ,  H01L27/11524 ,  H01L27/11519 ,  G11C16/04

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28008 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

公开(公告)号：US09613709B2

公开(公告)日：2017-04-04

申请号：US15276462

申请日：2016-09-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/027 ,  G11C16/14 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/02

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

公开(公告)号：US09461129B2

公开(公告)日：2016-10-04

申请号：US14854542

申请日：2015-09-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115 ,  H01L29/78 ,  G11C16/04 ,  H01L29/66

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

Abstract translation: 形成在半导体衬底中的存储单元包括在衬底中形成的沟槽中垂直延伸的选择栅极，并且通过栅极氧化物的第一层与衬底隔离，水平浮动栅极延伸在衬底上方并与衬底隔离，并与衬底隔离 栅极氧化物的第二层和在浮置栅极上方延伸的水平控制栅极。 选择栅极覆盖浮动栅极的侧面。 浮置栅极仅由第一层栅极氧化物与选择栅极分离，并且与垂直沟道区分离，仅沿着选择栅极在衬底中延伸，仅由栅极氧化物的第二层分离。

公开(公告)号：US20160181265A1

公开(公告)日：2016-06-23

申请号：US14854542

申请日：2015-09-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  G11C16/14 ,  G11C16/04

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

公开(公告)号：US20150348981A1

公开(公告)日：2015-12-03

申请号：US14671606

申请日：2015-03-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L21/28 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  G11C16/14 ,  H01L29/66

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28008 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储器，包括：第一存储单元，包括浮栅晶体管和具有嵌入垂直控制栅极的选择晶体管，第二存储单元包括浮栅晶体管和 选择具有与第一存储单元的选择晶体管相同的控制栅极的晶体管，耦合到第一存储单元的浮置栅晶体管的第一位线和耦合到第二存储器的浮置栅极晶体管的第二位线 细胞。

公开(公告)号：US09012961B2

公开(公告)日：2015-04-21

申请号：US14148257

申请日：2014-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Hélène Dalle-Houilliez

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  G11C16/04

CPC classification number: H01L27/11556 ,  G11C16/0433 ,  H01L27/11524 ,  H01L29/66666 ,  H01L29/7827

Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.

Abstract translation: 本公开涉及在半导体衬底中制造垂直栅极晶体管的方法，包括在衬底的深度中注入掺杂的隔离层，以形成晶体管的源极区域; 在衬底中形成垂直于沟槽隔离的平行沟槽隔离和第二沟槽，到达隔离层，并通过第一介电层与衬底隔离; 在所述衬底的表面和所述第二沟槽中沉积第一导电层; 蚀刻第一导电层以形成晶体管的垂直栅极，以及在垂直栅极的末端和衬底的边缘之间的垂直栅极连接焊盘，同时在每个连接焊盘和垂直栅极之间的第一导电层中保持连续区域 门; 以及在所述第二沟槽的每一侧上注入掺杂区域，以形成所述晶体管的漏极区域。