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    Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
    51.
    发明授权
    Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit 有权
    包括双镶嵌结构和集成电路的集成电路的制造方法

    公开(公告)号：US06313025B1

    公开(公告)日：2001-11-06

    申请号：US09385165

    申请日：1999-08-30

    申请人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

    发明人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

    IPC分类号： H01L2144

    CPC分类号： H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers. In an alternative embodiment, the grooves are formed before the via or contact openings.

    摘要翻译： 一种形成双镶嵌结构的方法。 该方法包括形成包括绝缘层的堆叠和在叠层上方形成两个掩模的停止层。 一个掩模用于在绝缘层中形成通孔或接触开口，并且第二掩模用于形成用于绝缘层中的互连的沟槽。 在替代实施例中，凹槽在通孔或接触开口之前形成。

    Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers
    52.
    发明授权
    Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
    包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构

    公开(公告)号：US06294807B1

    公开(公告)日：2001-09-25

    申请号：US09259001

    申请日：1999-02-26

    申请人： Sailesh Chittipeddi ,  Charles Walter Pearce

    发明人： Sailesh Chittipeddi ,  Charles Walter Pearce

    IPC分类号： H01L27108

    CPC分类号： H01L28/40 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185 ,  H01L27/0805 ,  H01L27/1085

    摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent difflusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.

    摘要翻译： 绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止了钽的杂散。 提供高介电常数。 绝缘结构的热稳定性提高。 绝缘结构可以包括在电容器或浅沟槽隔离结构中。 示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。 下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。 上电极可以是TiN层或多晶硅层。 示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。 浅沟槽中填充有氧化物，如TEOS。 可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

    Distributed communications system for reducing equipment down-time
    54.
    发明授权
    Distributed communications system for reducing equipment down-time 有权
    分布式通信系统，用于减少设备停机时间

    公开(公告)号：US06246325B1

    公开(公告)日：2001-06-12

    申请号：US09442688

    申请日：1999-11-18

    申请人： Sailesh Chittipeddi

    发明人： Sailesh Chittipeddi

    IPC分类号： G08B2100

    CPC分类号： H04L41/0681 ,  G06F11/006 ,  G06F11/0748 ,  G06F11/2294 ,  H04W8/26 ,  H04W88/02

    摘要： A system and method to more efficiently exchange information between a service provider, such as a semiconductor company, and its remote equipment units. The system capable of immediately handling a number of information items, each belonging to a different remote equipment unit is disclosed. The system includes a central controller configured for interfacing with a plurality of remote equipment units via a wireless network. The central controller is configured to receive information from each remote equipment unit via a wireless network. This information includes alarm conditions and corresponding requests for repair. Each of the remote equipment units is identified by a unique code which is included in the information transmitted to the computer to identity the source (i.e., identity of the transmitting remote equipment unit). The central controller uses the code of the transmitting remote equipment unit to retrieve the corresponding data record stored in its memory. The repair person identified in the selected data record is then contacted automatically, e.g., by wireless paging. The system may be programmed with a pre-determined routine maintenance schedule for each remote equipment unit. Based on this schedule, the system automatically contacts the appropriate repair person by wireless paging and dispatches the repair person to the corresponding remote equipment unit for routine maintenance. Thus, the down-time of the remote equipment unit is reduced because the alarm condition is immediately transmitted to the central controller and the corresponding repair person is contacted automatically. There is no undesired down-time before monitoring personnel notices the alarm condition and contacts the corresponding repair person.

    摘要翻译： 一种在诸如半导体公司的服务提供商与其远程设备单元之间更有效地交换信息的系统和方法。 公开了能够立即处理多个信息项的系统，每个信息项属于不同的远程设备单元。 该系统包括经由无线网络与多个远程设备单元进行接口配置的中央控制器。 中央控制器被配置为经由无线网络从每个远程设备单元接收信息。 此信息包括报警条件和相应的维修要求。 每个远程设备单元由唯一的代码标识，该唯一代码被包括在发送到计算机的信息中以识别源（即发送的远程设备单元的身份）。 中央控制器使用发送远程设备单元的代码来检索存储在其存储器中的相应数据记录。 然后，在所选择的数据记录中识别的维修人员例如通过无线寻呼自动地被联系。 可以用每个远程设备单元的预定的日常维护计划对该系统进行编程。 根据该时间表，系统通过无线寻呼自动联系相应的维修人员，并将维修人员派到相应的远程设备单元进行日常维护。 因此，由于将报警条件立即发送到中央控制器并且相应的维修人员被自动接触，所以远程设备单元的停机时间减少。 在监控人员注意到报警情况之前，没有不必要的停机时间，并与相应的维修人员联系。

    Bond pad design for integrated circuits
    56.
    发明授权
    Bond pad design for integrated circuits 有权
    用于集成电路的焊盘设计

    公开(公告)号：US06207547B1

    公开(公告)日：2001-03-27

    申请号：US09305766

    申请日：1999-05-05

    申请人： Sailesh Chittipeddi ,  Vivian Ryan

    发明人： Sailesh Chittipeddi ,  Vivian Ryan

    IPC分类号： H01L2144

    CPC分类号： H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

    摘要： The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer. It is believed that the inter-structural cooperation between these two layers provides a graded composite support structure that acts as a differential force transducer to buffer internal and bonding stresses within an integrated circuit.

    摘要翻译： 本发明提供一种用于集成电路中的接合焊盘支撑结构，该集成电路具有位于其上的接合焊盘。 在一个实施例中，接合焊盘支撑结构包括位于接合焊盘下方并且具有形成在其中的开口的支撑层。 接合焊盘支撑结构还包括位于导电层上并且至少部分地延伸到开口中以在开口的至少一部分上形成接合焊盘支撑表面的电介质层。 在一个实施例中，第一接合焊盘支撑层可以包括导电金属，并且第二接合焊盘支撑层可以包括电介质材料。 本发明提供了一种独特的接合焊盘结构，其中第一接合焊盘支撑层内的开口至少部分地被第二接合焊盘支撑层填充。 据信这两层之间的结构间协作提供了一种梯度复合支撑结构，其作为差分力传感器来缓冲集成电路内的内部和结合应力。

    Method of forming a multi-layered dual-polysilicon structure
    57.
    发明授权
    Method of forming a multi-layered dual-polysilicon structure 有权
    形成多层双晶硅结构的方法

    公开(公告)号：US06191017B1

    公开(公告)日：2001-02-20

    申请号：US09298068

    申请日：1999-04-22

    申请人： Sailesh Chittipeddi ,  Michael J. Kelly

    发明人： Sailesh Chittipeddi ,  Michael J. Kelly

    IPC分类号： H01L213205

    CPC分类号： H01L21/82345 ,  H01L21/823462

    摘要： A method of forming a multi-layered dual-polysilicon structure that forms a polysilicon gate prior to formation of an ion implantation barrier and that requires fewer steps, is more economical, and permits fabrication of more compact semiconductor circuits and devices than prior art methods.

    摘要翻译： 在形成离子注入屏障之前形成多晶硅栅极并且需要较少步骤的多层双重多晶硅结构的形成方法更经济，并且允许制造比现有技术方法更紧凑的半导体电路和器件。

    Bond pad for a flip-chip package
    58.
    发明授权
    Bond pad for a flip-chip package 有权
    用于倒装芯片封装的焊盘

    公开(公告)号：US6087732A

    公开(公告)日：2000-07-11

    申请号：US162247

    申请日：1998-09-28

    申请人： Sailesh Chittipeddi ,  Vivian Ryan

    发明人： Sailesh Chittipeddi ,  Vivian Ryan

    IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L24/02 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14

    摘要： A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

    摘要翻译： 接合焊盘支撑结构位于集成电路上的接合焊盘下方。 接合焊盘支撑结构包括至少部分地位于接合焊盘下方的第一接合焊盘支撑层。 第一接合焊盘支撑层具有多个径向图案，其具有在径向图案之间的至少一个空间。 径向图案可以是例如具有近似均匀厚度的直线。 或者，径向图案可以是三角形，每个三角形具有指向接合垫下方的区域的中心的顶点。 径向图案可以具有多个不同的长度。 第二接合焊盘支撑层位于第一接合焊盘支撑层上。 第二接合垫支撑层填充径向图案之间的空间的至少一部分。

    Transistor fabrication method
    59.
    发明授权
    Transistor fabrication method 有权
    晶体管制造方法

    公开(公告)号：US08030199B2

    公开(公告)日：2011-10-04

    申请号：US12689749

    申请日：2010-01-19

    申请人： Sailesh Chittipeddi ,  Taeho Kook ,  Avinoam Kornblit

    发明人： Sailesh Chittipeddi ,  Taeho Kook ,  Avinoam Kornblit

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S438/945

    摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

    摘要翻译： 公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。 使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。 可以形成各种硅化和非硅化的结构。