公开(公告)号：US10585630B2

公开(公告)日：2020-03-10

申请号：US15845985

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Vladimir Nikitin ,  Dmytro Apalkov

IPC: H01L21/822 ,  H01L27/22 ,  G06F3/06 ,  H01L27/11578 ,  H01L21/3105 ,  G11C11/16 ,  G11C11/18 ,  H01L43/08

Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.

公开(公告)号：US10566330B2

公开(公告)日：2020-02-18

申请号：US15977949

申请日：2018-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Palle ,  Rwik Sengupta ,  Mohammad Ali Pourghaderi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

公开(公告)号：US20190332943A1

公开(公告)日：2019-10-31

申请号：US16122789

申请日：2018-09-05

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan M. Hatcher

IPC: G06N3/08 ,  G06N3/04 ,  G06N5/04

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.

公开(公告)号：US10446400B2

公开(公告)日：2019-10-15

申请号：US15898420

申请日：2018-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/49

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US20190154493A1

公开(公告)日：2019-05-23

申请号：US15886753

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G01G23/38 ,  G11C7/10 ,  G06G7/16 ,  G11C13/00

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

公开(公告)号：US10170549B2

公开(公告)日：2019-01-01

申请号：US14918954

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/778

Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

公开(公告)号：US10164121B2

公开(公告)日：2018-12-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US09966137B2

公开(公告)日：2018-05-08

申请号：US15343182

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/54 ,  G11C11/56 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/00

Abstract: A neuron circuit for use in a neural network is disclosed. The neural network includes a plurality of field effect transistors having confined channels. The sources and drains of the field effect transistors are connected in series. A plurality of input terminals for receiving a plurality of input voltages may be connected to a drain terminal of a corresponding field effect transistor. The threshold voltages of the field effect transistors can be programmed by increasing or decreasing a number of excess minority carriers in the confined channels, thereby programming the resistance presented by the field effect transistor.

公开(公告)号：US09905672B2

公开(公告)日：2018-02-27

申请号：US15276784

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Reddy Palle ,  Joon Goo Hong

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US20180053690A1

公开(公告)日：2018-02-22

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/82345 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.