公开(公告)号：US20110108048A1

公开(公告)日：2011-05-12

申请号：US13001007

申请日：2008-06-24

申请人： Young-soo Park

发明人： Young-soo Park

IPC分类号： A45D24/14 ,  A45D24/00

CPC分类号： A45D24/14 ,  A45D24/00 ,  A45D24/02 ,  A45D24/30

摘要： A comb has a function for preventing slippage occurring when the comb is gripped, and allowing a user to remove a liquid adhered to the fingertips promptly. Further, the comb can be deformed flexibly. The comb has a concave-convex surface formed in a back face part of a comb main body, and the holes are formed in concave parts of the concave-convex surface. Curving surfaces are formed in side face parts on both sides of the comb main body, and through-holes communicating with the holes are formed in concave parts of the curving surface. When the user applies his/her fingers onto the back face part, the concave-convex surface and the holes function as a slippage preventing part. When applying the fingers onto the side face parts, the curving surface and the through-holes function as the slippage preventing part.

摘要翻译： 梳子具有防止梳子夹持时发生滑动的功能，并且允许使用者迅速地去除附着在指尖上的液体。 此外，梳子可以灵活地变形。 梳子具有形成在梳状主体的背面部分中的凹凸表面，并且孔形成在凹凸表面的凹部中。 弯曲表面形成在梳状主体两侧的侧面部分中，并且与孔相通的通孔形成在弯曲表面的凹部中。 当使用者将他/她的手指施加到背面部分上时，凹凸表面和孔用作防滑部分。 当将手指应用于侧面部分时，弯曲表面和通孔用作防滑部分。

公开(公告)号：US07910920B2

公开(公告)日：2011-03-22

申请号：US12005395

申请日：2007-12-27

申请人： Jae-chul Park ,  Young-soo Park ,  Sun-Il Kim

发明人： Jae-chul Park ,  Young-soo Park ,  Sun-Il Kim

IPC分类号： H01L29/08 ,  H01L51/00 ,  H01L29/10 ,  H01L29/12 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/7869 ,  H01L29/78609

摘要： A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.

公开(公告)号：US20110042669A1

公开(公告)日：2011-02-24

申请号：US12923472

申请日：2010-09-23

申请人： Sun-il Kim ,  Young-soo Park ,  Jae-chul Park

发明人： Sun-il Kim ,  Young-soo Park ,  Jae-chul Park

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/78696

摘要： A transistor may include: a gate insulting layer, a gate electrode formed on a bottom side of the gate insulating layer, a channel layer formed on a top side of the gate insulating layer, a source electrode that contacts a first portion of the channel layer, and a drain electrode that contacts a second portion of the channel layer. The channel layer may have a double-layer structure, including an upper layer and a lower layer. The upper layer may have a carrier concentration lower than that of the lower layer. The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.

摘要翻译： 晶体管可以包括：栅极绝缘层，形成在栅极绝缘层的底侧的栅电极，形成在栅极绝缘层的顶侧的沟道层，源极与沟道层的第一部分接触 以及与沟道层的第二部分接触的漏电极。 沟道层可以具有双层结构，包括上层和下层。 上层可以具有低于下层的载流子浓度。 上层可以掺杂载体受体以使电阻高于下层的电阻。

公开(公告)号：US07889552B2

公开(公告)日：2011-02-15

申请号：US12068409

申请日：2008-02-06

申请人： Jae-chul Park ,  Jae-woong Hyun ,  Young-soo Park ,  Sun-il Kim

发明人： Jae-chul Park ,  Jae-woong Hyun ,  Young-soo Park ,  Sun-il Kim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.

摘要翻译： 根据示例实施例的非易失性半导体器件可以包括半导体衬底上的多个存储单元和半导体衬底上的至少一个选择晶体管，其中所述至少一个选择晶体管可以设置在与所述多个存储单元不同的电平 。 所述至少一个选择晶体管可以分别经由第一触点和/或第三触点连接到数据线和/或电源线。 所述至少一个选择晶体管可以经由第二触点和/或第四触点连接到所述多个存储单元。 所述至少一个选择晶体管的有源层可以含有氧化物。 因此，根据示例性实施例的非易失性半导体器件可以包括具有减小的尺寸的选择晶体管。

公开(公告)号：US20110008920A1

公开(公告)日：2011-01-13

申请号：US12805821

申请日：2010-08-20

申请人： Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

发明人： Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

IPC分类号： H01L33/00 ,  H01L31/18

CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02327

摘要： A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion. The image sensor includes a microlens formed by a similar method and a photodiode having a cylindrical shape.

摘要翻译： 提供微透镜，包括微透镜的图像传感器，形成微透镜的方法和制造图像传感器的方法。 微透镜包括形成在基板上的具有圆柱形状的多晶硅图案和包围多晶硅图案的圆形外壳部分。 微透镜还可以包括填充壳体部分的内部的填充材料或覆盖第一壳体部分的第二壳体部分。 形成微透镜的方法包括在具有较低结构的半导体衬底上形成硅图案，在硅图案上的半导体衬底上形成覆盖膜，使硅图案和覆盖膜退火，将硅图案改变为具有 圆筒形，并且封盖膜用于圆形微透镜的外壳部分，并且通过半导体基板和外壳部分的边缘之间的开口用透镜材料填充外壳部分的内部。 图像传感器包括通过类似方法形成的微透镜和具有圆柱形状的光电二极管。

公开(公告)号：US07629207B2

公开(公告)日：2009-12-08

申请号：US11692716

申请日：2007-03-28

申请人： Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Young-kwan Cha

发明人： Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Young-kwan Cha

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78678 ,  H01L21/268 ,  H01L27/1285 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

摘要： A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

摘要翻译： 相对简单且容易地形成具有大晶粒尺寸的多晶沟道区的底栅薄膜晶体管（“TFT”）的制造方法。 制造底栅极薄膜晶体管的方法包括在衬底上形成底栅电极，在衬底上形成栅极绝缘层以覆盖底栅电极，形成非晶半导体层，N型半导体层和电极 依次在栅极绝缘层上蚀刻形成在底栅电极上的电极区域和N型半导体层区域，以暴露非晶半导体层区域，使用激光退火法熔化非晶半导体层区域，并使 熔融的非晶半导体层区域以形成横向生长的多晶沟道区域。

公开(公告)号：US20090298268A1

公开(公告)日：2009-12-03

申请号：US12457586

申请日：2009-06-16

申请人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

发明人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

IPC分类号： H01L21/336 ,  H01L21/205

CPC分类号： H01L21/02532 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02354 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/31608 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

摘要： A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a Si02 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 A or more. An interface trap density of the Si02 can be as high as lo∥/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

摘要翻译： 提供一种制造多晶硅薄膜的方法和使用其制造多晶硅TFT的方法。 使用ICP-CVD在低温下形成多晶硅薄膜。 在ICP-CVD之后，在通过预定步骤增加能量的同时执行ELA。 使用ICP-CVD在约150℃的温度下沉积多晶硅有源层和SiO 2栅极绝缘层。 多晶硅具有约3000A以上的大晶粒尺寸。 SiO 2的界面陷阱密度可以高达lo // / cm2。 具有良好电特性的晶体管可以在低温下制造，因此可以形成在耐热塑料基板上。

公开(公告)号：US20090184396A1

公开(公告)日：2009-07-23

申请号：US12289069

申请日：2008-10-20

申请人： Ki-hwan Kim ,  Young-soo Park ,  Myung-jae Lee ,  Xianyu Wenxu ,  Seung-eon Ahn ,  Chang-bum Lee

发明人： Ki-hwan Kim ,  Young-soo Park ,  Myung-jae Lee ,  Xianyu Wenxu ,  Seung-eon Ahn ,  Chang-bum Lee

IPC分类号： H01L27/02 ,  H01L21/441

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： Provided are resistive random access memories (RRAMs) and methods of manufacturing the same. A RRAM includes a storage node including a variable resistance layer, a switching device connected to the storage node, and a protective layer covering an exposed part of the variable resistance layer. The protective layer includes at least one of aluminum oxide and titanium oxide. The variable resistance layer is a metal oxide layer.

摘要翻译： 提供了电阻随机存取存储器（RRAM）及其制造方法。 RRAM包括存储节点，包括可变电阻层，连接到存储节点的开关装置和覆盖可变电阻层的暴露部分的保护层。 保护层包括氧化铝和氧化钛中的至少一种。 可变电阻层是金属氧化物层。

公开(公告)号：US20090146142A1

公开(公告)日：2009-06-11

申请号：US12076608

申请日：2008-03-20

申请人： Kyoung-kook Kim ,  Joo-sung Kim ,  Young-soo Park

发明人： Kyoung-kook Kim ,  Joo-sung Kim ,  Young-soo Park

IPC分类号： H01L33/00 ,  H01L21/205

CPC分类号： H01L33/08 ,  B82Y20/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/0262 ,  H01L33/34

摘要： Provided are a light-emitting device including a plurality of nanorods each of which comprises an active layer formed between an n-type region and a p-type region, and a method of manufacturing the same. The light-emitting device comprises: a substrate; a first electrode layer formed on the substrate; a basal layer formed on the first electrode layer; a plurality of nanorods formed vertically on the basal layer, each of which comprises a bottom part doped with first type, a top part doped with second type opposite to the first type, and an active layer between the bottom part and the top part, an insulating region formed between the nanorods, and a second electrode layer formed on the nanorods and the insulating region.

摘要翻译： 提供了包括多个纳米棒的发光器件及其制造方法，每个纳米棒包括形成在n型区域和p型区域之间的有源层。 发光装置包括：基板; 形成在所述基板上的第一电极层; 形成在所述第一电极层上的基底层; 在基底层上垂直形成的多个纳米棒，每个纳米棒包括掺杂有第一类型的底部部分，掺杂有与第一类型相反的第二类型的顶部部分，以及在底部部分和顶部部分之间的有源层， 形成在纳米棒之间的绝缘区域和形成在纳米棒和绝缘区域上的第二电极层。

公开(公告)号：US20090072246A1

公开(公告)日：2009-03-19

申请号：US12076308

申请日：2008-03-17

申请人： Stefanovich Genrikh ,  Bo-soo Kang ,  Young-soo Park ,  Xianyu Wenxu ,  Myoung-Jae Lee ,  Seung-eon Ahn ,  Chang-bum Lee

发明人： Stefanovich Genrikh ,  Bo-soo Kang ,  Young-soo Park ,  Xianyu Wenxu ,  Myoung-Jae Lee ,  Seung-eon Ahn ,  Chang-bum Lee

IPC分类号： H01L33/00

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/24 ,  H01L29/242 ,  H01L29/267 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： Provided are a diode and a memory device comprising the diode. The diode includes a p-type semiconductor layer and an n-type semiconductor layer, wherein at least one of the p-type semiconductor layer and the n-type semiconductor layer comprises a resistance changing material whose resistance is changed according to a voltage applied to the resistance changing material.

摘要翻译： 提供了二极管和包括二极管的存储器件。 二极管包括p型半导体层和n型半导体层，其中p型半导体层和n型半导体层中的至少一个包括电阻变化材料，其电阻根据施加到 电阻变化材料。