公开(公告)号：US20130093018A1

公开(公告)日：2013-04-18

申请号：US13272349

申请日：2011-10-13

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor.

摘要翻译： 一种方法包括提供具有设置在半导体层上的绝缘体层的半导体层的晶片。 绝缘体层具有在其中形成的开口以暴露半导体层的表面，其中每个开口对应于在栅叠层下方的半导体层中将成为晶体管沟道的位置。 该方法还包括沉积高介电常数栅极绝缘体层以覆盖半导体层的暴露表面和绝缘体层的侧壁; 沉积覆盖在高介电常数栅极绝缘体层上的栅极金属层; 以及通过栅极金属层和下面的高介电常数栅极绝缘体层注入碳以便在半导体层的上部形成具有选定的碳浓度的碳注入区域，以建立晶体管的电压阈值。

公开(公告)号：US20120306026A1

公开(公告)日：2012-12-06

申请号：US13118750

申请日：2011-05-31

申请人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field.

摘要翻译： 在替代栅极结构中采用钨阻挡部分以阻止材料从金属部分扩散到功函件材料部分。 钨阻挡部分有效地用作金属部分和功函材料部分之间的扩散阻挡层，使得功函数材料部分的组成不受包括替换栅极结构的场效应晶体管的退火和/或使用的影响。 因此，场效应晶体管的阈值电压可以在整个处理步骤和现场使用中保持稳定。

公开(公告)号：US20120292602A1

公开(公告)日：2012-11-22

申请号：US13111615

申请日：2011-05-19

申请人： DECHAO GUO ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： DECHAO GUO ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L51/10 ,  H01L51/40

CPC分类号： H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

摘要： A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

摘要翻译： 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅极电极，并且在掩埋栅电极上图案化包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20120139062A1

公开(公告)日：2012-06-07

申请号：US12958608

申请日：2010-12-02

申请人： Jun Yuan ,  Dechao Guo ,  Keith Kwong Hon Wong ,  Yanfeng Wang ,  Gan Wang

发明人： Jun Yuan ,  Dechao Guo ,  Keith Kwong Hon Wong ,  Yanfeng Wang ,  Gan Wang

IPC分类号： H01L29/772 ,  H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.

摘要翻译： 提供一种形成半导体器件的方法，其包括在衬底的部分上形成替换栅极结构，其中源极区和漏极区形成在衬底的形成有所述替换栅极结构的部分的相对侧上。 在具有与替换栅极结构的上表面共面的上表面的基板上形成层间电介质。 替换栅极结构被去除以提供到衬底的暴露部分的开口。 在开口的侧壁上形成高k电介质垫片，并且在衬底的暴露部分上形成栅极电介质。 通过孔内介电层形成触点到源区和漏区中的至少一个，其中为触点提供开口的蚀刻对高k电介质间隔物和高k电介质封盖层是选择性的。

公开(公告)号：US20120104469A1

公开(公告)日：2012-05-03

申请号：US12912963

申请日：2010-10-27

申请人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

发明人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

摘要翻译： 在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。 去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。 栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。

公开(公告)号：US20120043620A1

公开(公告)日：2012-02-23

申请号：US12860979

申请日：2010-08-23

申请人： Dechao Guo ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/78696 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

摘要： A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device.

摘要翻译： 一种用于制造场效应晶体管器件的方法包括形成第一导电沟道和第二导电沟道，在第一导电沟道上形成第一栅极叠层以部分地限定第一器件，在第二导电沟道上形成第二栅极堆叠以部分地限定 第二装置，注入离子以形成连接到第一导电沟道和第二导电沟道的源极区域和漏极区域，在第二器件上形成掩模层，源极区域的一部分和漏极区域的一部分，执行 第一退火处理，其可操作以改变第一器件的阈值电压，去除掩模层的一部分以暴露第二器件，以及执行可操作以改变第一器件的阈值电压的第二退火处理和第二器件的阈值电压 第二设备

公开(公告)号：US08084346B1

公开(公告)日：2011-12-27

申请号：US12908016

申请日：2010-10-20

申请人： Dechao Guo ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jun Yuan

发明人： Dechao Guo ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/2633 ,  H01L21/31105 ,  H01L29/6653

摘要： A method includes forming a dummy gate in a dielectric layer on a substrate, the dummy gate including a sacrificial oxide layer and a dummy gate body over the sacrificial oxide layer; removing the dummy gate body resulting in a gate opening with the sacrificial oxide layer in a bottom of the gate opening; performing an off-axis sputtering to create an angled entrance on the gate opening; removing the sacrificial oxide layer; and forming a replacement gate in the gate opening.

摘要翻译： 一种方法包括在基板上的电介质层中形成虚拟栅极，所述伪栅极包括在所述牺牲氧化物层上的牺牲氧化物层和虚设栅极; 在栅极开口的底部移除伪栅极体，导致栅极与牺牲氧化物层的开口; 执行离轴溅射以在门开口上形成成角度的入口; 去除牺牲氧化物层; 并在门开口中形成替换门。

公开(公告)号：US08767299B2

公开(公告)日：2014-07-01

申请号：US12906697

申请日：2010-10-18

申请人： Fei Liu ,  Qiqing C. Quyang ,  Keith Kwong Hon Wong

发明人： Fei Liu ,  Qiqing C. Quyang ,  Keith Kwong Hon Wong

IPC分类号： G02B5/18 ,  H01L21/30

CPC分类号： G02B5/18 ,  G02B5/1857 ,  G02B5/1866 ,  G02B6/124 ,  G02B2006/12107 ,  G03F7/2016 ,  H01L21/30

摘要： An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating.

摘要翻译： 嵌入式垂直光栅，包括嵌入式垂直光栅的半导体器件及其形成方法。 用于在衬底内形成嵌入式光栅的方法包括在衬底上沉积硬掩模层，图案化硬掩模层内的至少一个开口，垂直蚀刻衬底内对应于在该掩模层内的至少一个开口的多个扇贝 硬掩模层，去除硬掩模层，以及在多个扇贝内形成氧化物层以形成嵌入的垂直光栅。

公开(公告)号：US20120092771A1

公开(公告)日：2012-04-19

申请号：US12906697

申请日：2010-10-18

申请人： Fei Liu ,  Qiqing (Christine) Ouyang ,  Keith Kwong Hon Wong

发明人： Fei Liu ,  Qiqing (Christine) Ouyang ,  Keith Kwong Hon Wong

IPC分类号： G02B5/18 ,  H01L21/30

CPC分类号： G02B5/18 ,  G02B5/1857 ,  G02B5/1866 ,  G02B6/124 ,  G02B2006/12107 ,  G03F7/2016 ,  H01L21/30

摘要： An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating.

摘要翻译： 嵌入式垂直光栅，包括嵌入式垂直光栅的半导体器件及其形成方法。 用于在衬底内形成嵌入式光栅的方法包括在衬底上沉积硬掩模层，图案化硬掩模层内的至少一个开口，垂直蚀刻衬底内对应于在该掩模层内的至少一个开口的多个扇贝 硬掩模层，去除硬掩模层，以及在多个扇贝内形成氧化物层以形成嵌入的垂直光栅。

公开(公告)号：US09016236B2

公开(公告)日：2015-04-28

申请号：US12185339

申请日：2008-08-04

申请人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

发明人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

IPC分类号： H01L21/306 ,  C23C16/00 ,  C23C16/507 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  C23C16/458 ,  C23C16/56 ,  H01J37/20 ,  H01J37/32 ,  H01L27/108 ,  H01L21/316 ,  H01L21/318

CPC分类号： C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

摘要： A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an “electron filter” that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.

摘要翻译： 公开了一种高密度等离子体化学气相沉积工具和该工具的使用方法。 化学气相沉积工具允许对保持正在制造的衬底的基座进行角度调节。 电磁铁用作允许将材料角度沉积到衬底上的“电子过滤器”。 还公开了在半导体制造工艺中制造沟槽结构和不对称间隔物的方法。 角度沉积节省了工艺步骤，从而降低了制造时间，复杂性和成本，同时提高了整体产品的产量。