公开(公告)号：US20170011810A1

公开(公告)日：2017-01-12

申请号：US15272417

申请日：2016-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: G11C29/00 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C29/76 ,  G11C5/02 ,  G11C5/06 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/26 ,  G11C2213/71 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A three-dimensional flash memory system is disclosed.

Abstract translation: 公开了三维闪存系统。

公开(公告)号：US20160133639A1

公开(公告)日：2016-05-12

申请号：US14935201

申请日：2015-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L27/11526 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Abstract translation: 一种存储器件，具有每个具有单个连续沟道区的存储单元对，在沟道区的第一和第二部分上的第一和第二浮置栅极，位于第一和第二沟道区域之间的沟道区的第三部分上的擦除栅极， 以及第一和第二浮动栅极上的第一和第二控制栅极。 对于每对存储器单元，第一区域电连接到相同有源区域中相邻的一对存储器单元的第二区域，并且第二区域电连接到相邻存储器对的第一区域 细胞在相同的活性区域。

公开(公告)号：US20160099067A1

公开(公告)日：2016-04-07

申请号：US14506433

申请日：2014-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

公开(公告)号：US12249368B2

公开(公告)日：2025-03-11

申请号：US18645184

申请日：2024-04-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

公开(公告)号：US20240338144A1

公开(公告)日：2024-10-10

申请号：US18212066

申请日：2023-06-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  HOA VU ,  STANLEY HONG ,  THUAN VU

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/062 ,  G06F3/0679 ,  G11C16/08

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

公开(公告)号：US20240257880A1

公开(公告)日：2024-08-01

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US20240220154A1

公开(公告)日：2024-07-04

申请号：US18604884

申请日：2024-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06F3/06 ,  G06N3/065 ,  G11C7/10 ,  G11C7/16 ,  G11C11/54 ,  G11C27/00

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/065 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/54 ,  G11C27/005

Abstract: Numerous embodiments of an array of non-volatile memory cells are disclosed herein. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; wherein in a first mode, the array stores digital data; and wherein in a second mode, the array stores analog data.

公开(公告)号：US11989440B2

公开(公告)日：2024-05-21

申请号：US17519241

申请日：2021-11-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C7/16 ,  G06F3/06 ,  G06N3/065 ,  G11C7/10 ,  G11C11/54 ,  G11C27/00

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/065 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/54 ,  G11C27/005

Abstract: Numerous embodiments of a hybrid memory system are disclosed. The hybrid memory can store weight data in an array in analog form when used in an analog neural memory system or in digital form when used in a digital neural memory system. Input circuitry and output circuitry are capable of supporting both forms of weight data.

公开(公告)号：US11935594B2

公开(公告)日：2024-03-19

申请号：US17672617

申请日：2022-02-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G11C16/08 ,  G06N3/065 ,  G11C11/54

CPC classification number: G11C16/08 ,  G06N3/065 ,  G11C11/54

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

公开(公告)号：US11875852B2

公开(公告)日：2024-01-16

申请号：US17140924

申请日：2021-01-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G11C7/12 ,  G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.