公开(公告)号：US06380087B1

公开(公告)日：2002-04-30

申请号：US09596901

申请日：2000-06-19

申请人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L24/02 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10S438/926

摘要： A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.

摘要翻译： 一种制造具有至少一个集成电路的半导体晶片的方法，所述方法包括以下步骤。 提供了至少具有上介电层和下电介质层的半导体晶片结构。 该半导体晶片结构具有焊盘区域和互连区域。 具有第一宽度的至少一个有源互连通过电介质层形成在互连区域中。 通过电介质层的一部分，在焊盘区域中形成多个具有第二宽度的相邻虚拟插头。 对半导体晶片结构进行图案化和蚀刻，以形成通过上部电介质层的沟槽。 沟槽围绕至少一个有源互连和虚拟插头中的每一个，由此相邻虚拟插头之间的上部电介质层被去除。 金属化层沉积在下电介质层上，至少填充到剩余的上电介质层的上表面上的沟槽。 金属化层被平坦化以去除在焊盘区域内形成连续接合焊盘的多余的金属化层，并且包括多个相邻的虚设插头，从而形成包括至少一个相应的有源互连的至少一个镶嵌结构。

公开(公告)号：US06225221B1

公开(公告)日：2001-05-01

申请号：US09501966

申请日：2000-02-10

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76874 ,  H01L21/76876 ,  H01L2221/1089

摘要： A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.

摘要翻译： 已经实现了在制造集成电路器件中沉积铜种子层的新方法。 铜种子层薄且保形，非常适合随后的铜化学镀。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化的电介质层形成用于计划的双镶嵌互连的通孔和沟槽。 包含钽，钛或钨的阻挡层沉积在电介质层上，以对通孔和沟槽进行排列。 通过CuF2蒸汽与阻挡层的反应沉积覆盖阻挡层的铜籽晶层，并且集成电路完成。

公开(公告)号：US20050224921A1

公开(公告)日：2005-10-13

申请号：US11150879

申请日：2005-06-09

申请人： Subhash Gupta ,  Paul Ho ,  Sangki Hong

发明人： Subhash Gupta ,  Paul Ho ,  Sangki Hong

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L29/40 ,  H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit. In this case, the electrical conducting vias are also connected to various circuit elements by metallic conductors disposed in a dielectric layer that covers the circuit layer. A plurality of bonding pads are provided on one surface of the integrated circuit wafer. These pads may be part of the vias. These pads preferably extend above the surface of the integrated circuit wafer. A stacked integrated circuit according to the present invention is constructed by bonding two integrated circuit wafers together utilizing the bonding pads. One of the integrated circuit wafers is then thinned to a predetermined thickness determined by the depth of the vias by chemical/mechanical polishing (CMP) of the surface of that integrated circuit wafer that is not bonded to the other integrated circuit wafer, the stop layer in the vias preventing the CMP from removing wafer material that is within the first distance from the first surface of the substrate of the wafer being thinned.

摘要翻译： 一种集成电路晶片元件和用于将其结合以产生堆叠集成电路的改进方法。 根据本发明的集成电路晶片包括具有由晶片材料构成的第一和第二表面的基板，所述第一表面具有包括在其上构成的集成电路元件的电路层。 多个通孔从第一表面延伸穿过电路层，并在离开第一表面的第一距离处终止在基板中。 通孔包括位于每个通孔底部的停止层，该停止层由比晶片材料更耐化学/机械抛光（CMP）的止动材料构成。 通孔可以填充有导电材料，以在堆叠集成电路中的各个电路层之间提供垂直连接。 在这种情况下，导电通孔也通过布置在覆盖电路层的电介质层中的金属导体连接到各种电路元件。 多个接合焊盘设置在集成电路晶片的一个表面上。 这些焊盘可以是通孔的一部分。 这些焊盘优选地在集成电路晶片的表面上方延伸。 根据本发明的堆叠集成电路是通过使用接合焊盘将两个集成电路晶片结合在一起而构成的。 然后通过化学/机械抛光（CMP）将集成电路晶片之一变薄到由通孔的深度确定的预定厚度，该集成电路晶片的表面未结合到另一集成电路晶片，停止层 在通孔中，防止CMP从晶片的衬底的第一表面的第一距离内移除晶片材料。

公开(公告)号：US20060280698A1

公开(公告)日：2006-12-14

申请号：US11152499

申请日：2005-06-14

申请人： Subhash Gupta ,  Dennis Flanagan

发明人： Subhash Gupta ,  Dennis Flanagan

IPC分类号： A61K8/96 ,  A61K36/18

CPC分类号： A61Q11/00 ,  A61K8/97 ,  A61K36/18

摘要： A system for treating conditions of the periodontium, such as gingivitis and periodontitis, includes an Ayurvedic medicinal solution and an applicator for delivering the solution to the periodontium. The Ayurvedic medicinal solution utilizes herbal extracts to break-down bacteria which can inflame gum tissue. In one embodiment, the solution comprises approximately 1 gram of triphala extract for every 10 ml of glycerine. In another embodiment, the solution comprises approximately 1 gram of amla extract for every 10 ml of glycerine. The applicator for delivering the solution to the periodontium may either be in the form of a cotton swab-type wand, a pipette or a spray dispenser.

摘要翻译： 用于治疗牙周病例如牙龈炎和牙周炎的系统包括阿育吠陀药用溶液和用于将溶液递送到牙周膜的施用器。 阿育吠陀药用溶液利用草药提取物分解可以使牙龈组织发炎的细菌。 在一个实施方案中，该溶液包含每10ml甘油约1克的三菌属提取物。 在另一个实施方案中，该溶液包含每10ml甘油约1克的amla提取物。 用于将溶液递送到牙周组织的施用器可以是棉签式棒，移液管或喷雾分配器的形式。

公开(公告)号：US20050181081A1

公开(公告)日：2005-08-18

申请号：US10761804

申请日：2004-01-21

申请人： Suman Khanuja ,  Pushplata Chaturvedi ,  Anil Singh ,  Ajit Shasany ,  Vinay Agarwal ,  Vivek Gupta ,  Subhash Gupta ,  Arun Tripathy ,  Anirban Pal ,  Dharmendra Saikia ,  Mahendra Darokar ,  Krishna Aggarwal ,  Ravi Bansal

发明人： Suman Khanuja ,  Pushplata Chaturvedi ,  Anil Singh ,  Ajit Shasany ,  Vinay Agarwal ,  Vivek Gupta ,  Subhash Gupta ,  Arun Tripathy ,  Anirban Pal ,  Dharmendra Saikia ,  Mahendra Darokar ,  Krishna Aggarwal ,  Ravi Bansal

IPC分类号： A61K36/00 ,  A61K36/534 ,  A61K36/54 ,  A61K36/8962 ,  A61K35/78

CPC分类号： A61K36/54 ,  A61K36/534 ,  A61K36/8962 ,  A61K2300/00

摘要： The present invention provides an improved preparation based on the synergistic action of garlic extract and essential oil of M. spicata var. Ganga or cinnamon oil against dermatophytic fungus. More particularly, the present invention relates to the synergistic enhancement of activity of a combination by menthyl acetate or Geraniol. The invention also provides a method of preparation of the synergistic combination and the shelf life observed to be more than one year. The cream based preparation is a potent anti-dermatophytic as described and illustrated by in vitro and in vivo evaluations.

摘要翻译： 本发明提供了一种改进的制剂，其基于大蒜提取物和M.spicata var。的精油的协同作用。 甘草或肉桂油抗皮肤真菌。 更具体地，本发明涉及通过乙酸薄荷酯或香叶醇组合的协同增强活性。 本发明还提供了一种制备协同组合的方法和观察到的一年以上的保质期。 基于乳膏的制剂是有效的抗皮肤真菌病，如通过体外和体内评价所描述和说明的。

公开(公告)号：US20050100610A1

公开(公告)日：2005-05-12

申请号：US10822790

申请日：2004-04-13

申请人： Suman Khanuja ,  Sushil Kumar ,  Ajit Shasany ,  Jai Arya ,  Mahendra Darokar ,  Monika Singh ,  Prachi Sinha ,  Soumya Awasthi ,  Subhash Gupta ,  Vivek Gupta ,  Madan Gupta ,  Ram Verma ,  Sweta Agarwal ,  Sunil Mansinghka ,  Suresh Dawle

发明人： Suman Khanuja ,  Sushil Kumar ,  Ajit Shasany ,  Jai Arya ,  Mahendra Darokar ,  Monika Singh ,  Prachi Sinha ,  Soumya Awasthi ,  Subhash Gupta ,  Vivek Gupta ,  Madan Gupta ,  Ram Verma ,  Sweta Agarwal ,  Sunil Mansinghka ,  Suresh Dawle

IPC分类号： A61K35/22 ,  A61K45/06 ,  A61P31/00 ,  A61P35/00 ,  A61K33/40 ,  A61K31/4965 ,  A61K31/4709 ,  A61K31/496 ,  A61K31/65

CPC分类号： A61K45/06 ,  A61K35/22 ,  A61K2300/00

摘要： The invention relates to a novel pharmaceutical composition comprising an effective amount of bio-active fraction from cow urine distillate as a bioavailability facilitator and pharmaceutically acceptable additives selected from anticancer compounds, antibiotics, drugs, therapeutic and nutraceutic agents, ions and similar molecules which are targeted to the living systems.

摘要翻译： 本发明涉及一种新型药物组合物，其包含有效量的来自牛尿馏分的生物活性级分作为生物利用度促进剂和选自抗癌化合物，抗生素，药物，治疗和营养药物，离子和类似分子的药学上可接受的添加剂 到生活系统。

公开(公告)号：US06331732B1

公开(公告)日：2001-12-18

申请号：US09439948

申请日：1999-11-12

申请人： Subhash Gupta ,  Susan Hsuching Chen

发明人： Subhash Gupta ,  Susan Hsuching Chen

IPC分类号： H01L2348

CPC分类号： H01L21/76877 ,  H01L21/76802

摘要： A method and system for providing a via structure for an integrated circuit is disclosed. The method and system includes providing a high conductivity metal that forms a metal structure consisting of the high conductivity metal. The method and system also includes a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole. The method and system also include providing a via plug material other than the high conductivity metal. The via plug material covers the high conductivity metal and substantially fills the via hole. The via plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is for gettering the high conductivity metal sputtered on the sidewalls of the via hole.

摘要翻译： 公开了一种用于提供用于集成电路的通孔结构的方法和系统。 该方法和系统包括提供形成由高导电性金属组成的金属结构的高导电性金属。 该方法和系统还包括围绕高导电性金属的电介质材料。 电介质材料包括形成通孔的侧壁。 该方法和系统还包括提供除了高导电性金属之外的通孔插塞材料。 通孔塞材料覆盖高导电性金属并且基本上填充通孔。 通孔插塞材料基本上覆盖高导电性金属的基部和通孔的侧壁。 通孔插塞材料用于吸收溅射在通孔侧壁上的高导电性金属。

公开(公告)号：US06232048B1

公开(公告)日：2001-05-15

申请号：US09260790

申请日：1999-03-01

申请人： Matthew S. Buynoski ,  Che-Hoo Ng ,  Bhanwar Singh ,  Shekhan Pramanick ,  Subhash Gupta

发明人： Matthew S. Buynoski ,  Che-Hoo Ng ,  Bhanwar Singh ,  Shekhan Pramanick ,  Subhash Gupta

IPC分类号： G03C500

CPC分类号： G03F7/40 ,  G03F7/2024 ,  G03F7/203 ,  H01L21/0274

摘要： A method of preparing a narrow photoresist line by first forming a resist pattern on a substrate, wherein a resist line is designed to have a width “w” in excess of a desired width “w1” The resist is then subjected to ionic bombardment with ionized particles in a direction normal to the planar surface of a resistant substrate. The ionic bombardment causes formation of a hardened “chemically less reactive” skin on the exposed top surface of the photoresist. The resist is then subjected to an isotropic etch procedure. Due to the hardened top surface of the narrow pattern, the side wall erode at a faster rate than the top, causing a narrowing of the line width, while retaining a more substantial photoresist thickness than would occur if the top surface would not be hardened in advance of the etch procedure.

摘要翻译： 一种通过在衬底上首先形成抗蚀剂图案来制备窄光致抗蚀剂线的方法，其中抗蚀剂线被设计成具有超过所需宽度“w1”的宽度“w”。然后将抗蚀剂用离子轰击 颗粒在垂直于耐磨基材的平坦表面的方向上。 离子轰击导致在光致抗蚀剂的暴露的顶表面上形成硬化的“化学反应性较差”的皮肤。 然后对抗蚀剂进行各向同性蚀刻程序。 由于狭窄图案的硬化顶表面，侧壁以比顶部更快的速度侵蚀，导致线宽度变窄，同时保留比如果顶表面不会硬化时更可观察到的光致抗蚀剂厚度 蚀刻过程的进步。

公开(公告)号：US6066578A

公开(公告)日：2000-05-23

申请号：US980888

申请日：1997-12-01

申请人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

发明人： Subhash Gupta ,  Bhanwar Singh ,  Carmen Morales

IPC分类号： G03F7/16 ,  H01L21/027 ,  H01L21/311 ,  H01L21/312 ,  G03C5/00

CPC分类号： G03F7/16 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/0274 ,  H01L21/3124

摘要： A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

公开(公告)号：US5746884A

公开(公告)日：1998-05-05

申请号：US696774

申请日：1996-08-13

申请人： Subhash Gupta ,  Robert Flores ,  Michael Ross Stamm ,  Eric Thomas Sharp ,  Erich W. E. Denninger ,  Pamela G. Dye ,  Joel Samuel Utz ,  James K. Kai

发明人： Subhash Gupta ,  Robert Flores ,  Michael Ross Stamm ,  Eric Thomas Sharp ,  Erich W. E. Denninger ,  Pamela G. Dye ,  Joel Samuel Utz ,  James K. Kai

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/00

CPC分类号： H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via extends a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via. The second stage includes a second sidewall stage extending from the first sidewall stage at a second angle between 40.degree. and 70.degree.. A third etch step is then performed to further remove portions of the dielectric layer to form a third and final stage of the fluted via. The fluted via extends from an upper surface of the dielectric layer to an upper surface of the first conductive layer. The third stage includes a third stage sidewall extending from said second stage sidewall to said upper surface of said first conductive layer at an angle between 60.degree. and 80.degree..

摘要翻译： 一种在半导体器件的层间电介质中形成通孔的方法，其中通孔具有带槽纹的侧壁。 提供具有形成在其上的第一导电层的半导体衬底。 然后在第一导电层上形成电介质层。 在介电层上沉积光致抗蚀剂层，并且在光致抗蚀剂层中形成接触开口以暴露电介质层的接触区域。 执行第一蚀刻步骤以去除接近接触区域的电介质层的部分，以形成槽纹通孔的第一级。 第一级包括从电介质层的上表面以小于50°的角度延伸的第一侧壁级。 槽纹通孔的第一级延伸第一横向距离，其大于接触开口的横向尺寸。 然后执行第二蚀刻步骤以进一步去除介电层的部分以形成槽纹通孔的第二级。 第二阶段包括从第一侧壁台以40°至70°之间的第二角度延伸的第二侧壁台。 然后执行第三蚀刻步骤以进一步去除介电层的部分以形成槽纹通孔的第三和最后一级。 带槽通孔从电介质层的上表面延伸到第一导电层的上表面。 第三级包括第三级侧壁，从第二级侧壁延伸至所述第一导电层的上表面，角度为60°至80°。