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    Structure for optionally cascading shift registers
    51.
    发明授权
    Structure for optionally cascading shift registers 有权
    可选择级联移位寄存器的结构

    公开(公告)号：US6118298A

    公开(公告)日：2000-09-12

    申请号：US253313

    申请日：1999-02-18

    申请人： Trevor J. Bauer ,  Bruce A. Newgard ,  William E. Allaire ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Bruce A. Newgard ,  William E. Allaire ,  Steven P. Young

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： G11C19/00 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17768

    摘要： A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series. The lookup table decode logic plus additional multiplexers can be used to select any memory cell (not necessarily the last memory cell) of the shift register.

    摘要翻译： 一组逻辑元件可以配置为可级联移位寄存器。 在一个实施例中，用于FPGA的逻辑元件可以被配置为随机存取存储器，级联移位寄存器和查找表中的任何一个。 到移位寄存器的数据输入路径包括级联多路复用器，用于可选地使用多个逻辑元件形成大移位寄存器。 每个逻辑元件包括互连的多个存储器单元，使得每个存储器单元的数据输出可以用作到下一个存储单元的输入，使逻辑元件用作移位寄存器。 级联多路复用器允许一个逻辑元件的最后一位连接到下一个逻辑元件的第一位，绕过查找表的任何解码逻辑。 可以通过串联多个逻辑元件的查询表来创建任意长度的可变抽头移位寄存器。 查找表解码逻辑加上附加多路复用器可用于选择移位寄存器的任何存储单元（不一定是最后一个存储单元）。

    Interconnect structure for FPGA with configurable delay locked loop
    52.
    发明授权
    Interconnect structure for FPGA with configurable delay locked loop 有权
    具有可配置延迟锁定环的FPGA的互连结构

    公开(公告)号：US6107826A

    公开(公告)日：2000-08-22

    申请号：US136461

    申请日：1998-08-19

    申请人： Steven P. Young ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Trevor J. Bauer

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1774

    摘要： A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have multiple pads as inputs. Programmable connections also enable the DLLs to be selectively connected to one another. Programmable connections further enable the pads to be selectively connected to general interconnect circuitry or global clock drivers of the FPGA. Programmable connections are also provided for selectively connecting the DLLs to the global clock drivers. This FPGA structure enables the pads to be configured to receive either clock or non-clock signals. This structure also enables the FPGA to operate as a clock mirror, and to generate one clock signal from another clock signal on the FPGA.

    摘要翻译： 提供了包括多个焊盘和多个延迟锁定环（DLL）的现场可编程门阵列（FPGA）。 可编程连接使得任何一个DLL具有多个焊盘作为输入。 可编程连接还使得可以将DLL选择性地彼此连接。 可编程连接进一步使焊盘能够选择性地连接到FPGA的通用互连电路或全局时钟驱动器。 还提供了可编程连接，用于选择性地将DLL连接到全局时钟驱动器。 该FPGA结构使焊盘能够配置为接收时钟或非时钟信号。 该结构还使FPGA能够作为时钟镜来工作，并从FPGA上的另一个时钟信号产生一个时钟信号。

    Apparatus for indirect impingement cooling of integrated circuit chips
    53.
    发明授权
    Apparatus for indirect impingement cooling of integrated circuit chips 失效
    用于集成电路芯片的间接冲击冷却的装置

    公开(公告)号：US5294830A

    公开(公告)日：1994-03-15

    申请号：US703614

    申请日：1991-05-21

    申请人： Steven P. Young ,  John Acocella ,  Albert J. Fahey ,  Gaetano P. Messina ,  Seaho Song

    发明人： Steven P. Young ,  John Acocella ,  Albert J. Fahey ,  Gaetano P. Messina ,  Seaho Song

    IPC分类号： H01L23/433 ,  H01L23/473 ,  H01L23/02 ,  H01L25/04

    CPC分类号： H01L23/4735 ,  H01L23/4338 ,  H01L2224/16225 ,  H01L2924/15312

    摘要： An integrated circuit thermal conduction module comprises a substrate having a chip-carrying surface and at least one integrated circuit chip on the substrate. A deformable, liquid-impermeable, thermally conductive film or foil extends over an upper surface of the chip. A piston has a lower surface which urges and conforms the film against the chip upper surface and which contains at least one open channel permitting coolant passage and contact with the film for conveying heat from the chip without direct contact between the coolant and chip. Preferably, the piston has a central passageway extending along the longitudinal axis for channeling the coolant through the piston, and has a plurality of channels extending radially outwardly from the central passageway along the lower face for directing coolant beneath the piston.

    摘要翻译： 集成电路热传导模块包括具有芯片承载表面的衬底和在衬底上的至少一个集成电路芯片。 可变形的液体不可渗透的导热膜或箔在芯片的上表面上延伸。 活塞具有下表面，该下表面促使薄膜抵靠芯片上表面，并且其包含至少一个敞开的通道，允许冷却剂通过并与薄膜接触，用于从芯片传送热量，而不会直接接触冷却剂和芯片。 优选地，活塞具有沿着纵向轴线延伸的中心通道，用于将冷却剂引导通过活塞，并且具有沿着下表面从中心通道径向向外延伸的多个通道，用于将冷却剂引导到活塞下方。

    Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same
    56.
    发明授权
    Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same 有权
    利用统一的逻辑块阵列的乘法体系结构及其使用方法

    公开(公告)号：US08527572B1

    公开(公告)日：2013-09-03

    申请号：US12417007

    申请日：2009-04-02

    申请人： Steven P. Young ,  Brian C. Gaide

    发明人： Steven P. Young ,  Brian C. Gaide

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/00 ,  G06F7/49994 ,  G06F7/57 ,  G06F2207/3864

    摘要： In a multiplier architecture, all stages of a multiplication function are implemented using a uniform array of logic blocks. An exemplary multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each logic block includes a multiply block and a logic circuit driven by the multiply block. The logic circuit is coupled to implement an add function. A first portion of the array is coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output. A second portion is coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output. The multiply blocks may be non-uniform arrays, e.g., logical AND gates and full adders in all but one column, with only logical AND gates in the remaining column.

    摘要翻译： 在乘法器架构中，乘法函数的所有阶段都使用统一的逻辑块阵列来实现。 示例性乘法器电路包括基本相似的逻辑块的二维阵列。 每个逻辑块包括乘法块和乘法块驱动的逻辑电路。 逻辑电路被耦合以实现加法功能。 阵列的第一部分被耦合以接收第一和第二被乘数输入，以提供部分乘积总线，并提供产品输出的较低位。 第二部分被耦合以从阵列的第一部分接收部分乘积总线，并且从部分乘积总线提供产品输出的较高位。 乘法块可以是除了一列之外的不均匀的阵列，例如逻辑与门和全加法器，在剩余的列中只有逻辑与门。

    Formation of columnar application specific circuitry using a columnar programmable device
    58.
    发明授权
    Formation of columnar application specific circuitry using a columnar programmable device 有权
    使用柱状可编程器件形成柱状应用专用电路

    公开(公告)号：US07965102B1

    公开(公告)日：2011-06-21

    申请号：US12248668

    申请日：2008-10-09

    申请人： Trevor J. Bauer ,  Steven P. Young

    发明人： Trevor J. Bauer ,  Steven P. Young

    IPC分类号： H01L25/00

    CPC分类号： G06F17/5054 ,  H03K19/177

    摘要： A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PD design to the columnar ASIC-like design.

    摘要翻译： 描述了转换为柱状专用集成电路（ASIC）设计的柱状可编程器件（PD）设计。 在具有与柱状PD设计相关联的柱状结构的PD中实例化用户设计。 柱状架构具有相邻的电路列，并且识别与PD中的用户设计的实例化相关联的一个或多个电路列。 一个或多个所标识的列的至少一部分与应用专用电路交换，用于实现用于将柱状PD设计转换成柱状ASIC样设计的全部或部分用户设计。

    Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same
    60.
    发明授权
    Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same 有权
    集成电路中用于逻辑块的级联控制信号的输出结构及其使用方法

    公开(公告)号：US07746112B1

    公开(公告)日：2010-06-29

    申请号：US12417043

    申请日：2009-04-02

    申请人： Brian C. Gaide ,  Steven P. Young

    发明人： Brian C. Gaide ,  Steven P. Young

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/17736

    摘要： A cascading output structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes an array of interconnected logic blocks, each including a logic circuit, an output multiplexer, and a select multiplexer. The logic circuit has an input coupled to a logic block input. The output multiplexer has first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input, and an output coupled to a logic block output. The select multiplexer has a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the output multiplexer. The output of the select multiplexer is also coupled to a cascade select output of the logic block. The cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block.

    摘要翻译： 集成电路中逻辑块的级联输出结构。 示例性集成电路包括互连的逻辑块的阵列，每个逻辑块包括逻辑电路，输出多路复用器和选择多路复用器。 逻辑电路具有耦合到逻辑块输入的输入。 输出多路复用器具有分别耦合到逻辑电路的第一和第二输出的第一和第二数据输入，选择输入和耦合到逻辑块输出的输出。 选择多路复用器具有耦合到逻辑块的级联选择输入的第一数据输入，第二数据输入和耦合到输出多路复用器的选择输入的输出。 选择多路复用器的输出也耦合到逻辑块的级联选择输出。 逻辑块的级联选择输入耦合到相邻逻辑块的级联选择输出。