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51.发明申请公开(公告)号：US20240373642A1
公开(公告)日：2024-11-07
申请号：US18777932
申请日：2024-07-19
Inventor： Yen-Chieh Huang , Po-Ting Lin , Song-Fu Liao , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.
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公开(公告)号：US20240347632A1
公开(公告)日：2024-10-17
申请号：US18756682
申请日：2024-06-27
Inventor： Yen-Chieh Huang , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC: H01L29/78 , H01L29/49 , H01L29/786 , H10B51/20
CPC classification number: H01L29/78391 , H01L29/4908 , H01L29/78642 , H01L29/78693 , H10B51/20
Abstract: A semiconductor device is described. The semiconductor device includes a blocking layer disposed on a channel of a substrate, a first seed layer disposed on the blocking layer, and a ferroelectric gate layer formed on the first seed layer. The first seed layer is arranged to increase a ratio of (O+T+C)/(O+T+C+M), in which O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.
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公开(公告)号：US20240347608A1
公开(公告)日：2024-10-17
申请号：US18299691
申请日：2023-04-12
Inventor： Yi-Cheng Chu , Chien-Hua Huang , Katherine H. CHIANG , Yu-Ming Lin , Chung-Te Lin
IPC: H01L29/417 , H01L23/522 , H01L29/40 , H01L29/66 , H01L29/786
CPC classification number: H01L29/41733 , H01L23/5226 , H01L29/401 , H01L29/66969 , H01L29/78606 , H01L29/7869
Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconducting material layer, a gate electrode under the semiconducting material layer, a pair of contact terminals over the semiconducting material layer, and a hydrogen-blocking dielectric layer on the semiconducting material layer. The pair of contact terminals penetrates through the hydrogen-blocking dielectric layer to be in contact with the semiconducting material layer at a contact surface, and the contact surface is substantially coplanar with and levelled with an interface between the hydrogen-blocking dielectric layer and the semiconducting material layer.
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公开(公告)号：US12119402B2
公开(公告)日：2024-10-15
申请号：US18308791
申请日：2023-04-28
Inventor： Yen-Chieh Huang , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC: H01L29/78 , H01L29/49 , H01L29/786 , H10B51/20
CPC classification number: H01L29/78391 , H01L29/4908 , H01L29/78642 , H01L29/78693 , H10B51/20
Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.
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公开(公告)号：US12114507B2
公开(公告)日：2024-10-08
申请号：US18335167
申请日：2023-06-15
Inventor： Rainer Yen-Chieh Huang , Hai-Ching Chen , Chung-Te Lin
IPC: H10B51/30 , H01L21/28 , H01L23/522 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/786 , H10B51/00
CPC classification number: H10B51/30 , H01L23/5226 , H01L29/40111 , H01L29/516 , H01L29/66765 , H01L29/6684 , H01L29/78391 , H01L29/78648 , H01L29/78669 , H01L29/78678 , H01L29/78687 , H01L29/7869 , H01L29/78693 , H10B51/00
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.
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Patent Agency Ranking
公开(公告)号：US12108605B2
公开(公告)日：2024-10-01
申请号：US17891152
申请日：2022-08-19
Inventor： Chieh-Fang Chen , Feng-Cheng Yang , Chung-Te Lin
CPC classification number: H10B51/20 , H01L29/6684 , H01L29/78391 , H10B51/10
Abstract: A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.
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公开(公告)号：US12058869B2
公开(公告)日：2024-08-06
申请号：US17837982
申请日：2022-06-10
Inventor： Bo-Feng Young , Han-Jong Chia , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC: H10B51/20 , H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L29/66 , H01L29/78 , H10B10/00 , H10B51/30 , H10B51/40
CPC classification number: H10B51/20 , H01L21/76898 , H01L21/8221 , H01L23/481 , H01L27/0688 , H01L29/66795 , H01L29/6684 , H01L29/78391 , H01L29/785 , H10B10/12 , H10B51/30 , H10B51/40
Abstract: The present disclosure provides a semiconductor structure, including a first layer including a logic device, a second layer over the first layer including a first type memory device, and a though silicon via (TSV) electrically connecting the logic device and the first type memory device.
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公开(公告)号：US20240099149A1
公开(公告)日：2024-03-21
申请号：US18520427
申请日：2023-11-27
Inventor： Yu-Feng Yin , Min-Kun Dai , Chien-Hua Huang , Chung-Te Lin
IPC: H10N50/01 , G11C11/16 , H01L21/768 , H01L23/522 , H10B61/00 , H10N50/80 , H10N50/85
CPC classification number: H10N50/01 , G11C11/161 , H01L21/76832 , H01L21/7684 , H01L21/76879 , H01L23/5226 , H10B61/00 , H10N50/80 , H10N50/85
Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
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公开(公告)号：US20240090226A1
公开(公告)日：2024-03-14
申请号：US18518579
申请日：2023-11-23
Inventor： Sheng-Chih Lai , Chung-Te Lin
IPC: H10B43/35 , H01L23/522 , H10B43/10 , H10B43/20
CPC classification number: H10B43/35 , H01L23/5226 , H10B43/10 , H10B43/20 , H01L2924/1438 , H01L2924/145
Abstract: A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.
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公开(公告)号：US20240015979A1
公开(公告)日：2024-01-11
申请号：US18472187
申请日：2023-09-21
Inventor： Chia-Yu Ling , Katherine H. CHIANG , Chung-Te Lin
CPC classification number: H10B51/30 , H10B51/20 , H10B51/10 , H01L29/6684 , H01L29/66742 , H10B51/40
Abstract: A method of manufacturing a memory cell includes the following steps. A channel material is formed to contact a source line and a bit line. A ferroelectric (FE) material is formed to contact the channel material. A word line is formed to contact the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.
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