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    TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
    52.
    发明申请
    TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS 审中-公开
    TSV测试使用测试电路和接地装置

    公开(公告)号：US20160282411A1

    公开(公告)日：2016-09-29

    申请号：US15176874

    申请日：2016-06-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Baher S. Haroun

    IPC: G01R31/3177 ,  G01R31/317

    CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318577

    Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

    Abstract translation: 本公开描述了一种用于测试半导体器件内的TSV的新颖方法和装置。 根据本公开中所示和描述的实施例，可以通过刺激和测量来自TSV的第一端的响应来测试TSV，同时TSV的第二端保持在地电位。 根据本公开，可以并行测试半导体器件内的多个TSV以减少TSV测试时间。

    Dielectric Waveguide Radar Signal Distribution
    53.
    发明申请
    Dielectric Waveguide Radar Signal Distribution 审中-公开
    介质波导雷达信号分布

    公开(公告)号：US20160240907A1

    公开(公告)日：2016-08-18

    申请号：US14969392

    申请日：2015-12-15

    Applicant: Texas Instruments Incorporated

    Inventor： Baher S. Haroun

    IPC: H01P3/16 ,  G01S7/03 ,  H01Q1/32

    CPC classification number: H01P3/16 ,  G01S7/032 ,  G01S7/034 ,  G01S13/931 ,  G01S2013/9375 ,  G01S2013/9378 ,  G01S2013/9385 ,  G01S2013/9389 ,  H01Q1/3233

    Abstract: A system is provided for transmitting sub-terahertz electro-magnetic radio frequency (RF) signals using a dielectric waveguide (DWG) having a dielectric core member surrounded by dielectric cladding. Multiple radar signals may be generated by a radar module that is coupled to a vehicle. A set of DWG segments may be used to transport the radar signals to various launching structures placed in various locations of the vehicle.

    Abstract translation: 提供一种用于使用具有由电介质包层围绕的介质芯构件的电介质波导（DWG）发射亚太赫兹电磁射频（RF）信号的系统。 可以由耦合到车辆的雷达模块产生多个雷达信号。 可以使用一组DWG段来将雷达信号传输到放置在车辆的各个位置的各种发射结构。

    THIRD TAP CIRCUITRY CONTROLLING LINKING FIRST AND SECOND TAP CIRCUITRY
    54.
    发明申请
    THIRD TAP CIRCUITRY CONTROLLING LINKING FIRST AND SECOND TAP CIRCUITRY 审中-公开
    第三个TAP电路控制连接第一和第二TAP电路

    公开(公告)号：US20160231380A1

    公开(公告)日：2016-08-11

    申请号：US15134877

    申请日：2016-04-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/3177 ,  G01R31/317

    CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

    Relaxation oscillator with current and voltage offset cancellation
    55.
    发明授权
    Relaxation oscillator with current and voltage offset cancellation 有权
    具有电流和电压偏移消除的松弛振荡器

    公开(公告)号：US09356554B2

    公开(公告)日：2016-05-31

    申请号：US14329939

    申请日：2014-07-12

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Yiu Tam ,  Ali Kiaei ,  Baher S. Haroun

    IPC: H03K3/30 ,  H03B5/04 ,  H03K4/50 ,  H03K4/02 ,  H03B5/24

    CPC classification number: H03B5/04 ,  H03B5/24 ,  H03K3/0231 ,  H03K4/023 ,  H03K4/50 ,  H03K4/502 ,  H03K4/94

    Abstract: A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so that after the first current has been input to a first pair of circuits and the second current has been input to a second pair of circuits, the second current is input to the first pair of circuits and the first current is input to the second pair of circuits.

    Abstract translation: 松弛振荡器通过周期性交换第一电流和第二电流来降低在低偏移频率下的温度灵敏度和相位噪声，使得在第一电流已经被输入到第一对电路之后，并且第二电流已经被输入到第二对 电路，第二电流被输入到第一对电路，第一电流被输入到第二对电路。

    IC with connections between linking module and test access ports
    56.
    发明授权
    IC with connections between linking module and test access ports 有权
    IC连接在连接模块和测试访问端口之间

    公开(公告)号：US08977918B2

    公开(公告)日：2015-03-10

    申请号：US14460824

    申请日：2014-08-15

    Applicant: Texas Instruments Incorporated

    Inventor： Baher S. Haroun ,  Lee D. Whetsel

    IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/46

    CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    Abstract translation: 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

    TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    58.
    发明申请
    TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS 有权
    用于IEEE 1149.1测试访问端口的多个光纤扫描接入的TAP和链接模块

    公开(公告)号：US20140040689A1

    公开(公告)日：2014-02-06

    申请号：US14044535

    申请日：2013-10-02

    Applicant: Texas Instruments Incorporated

    Inventor： Baher S. Haroun ,  Lee D. Whetsel

    IPC: G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    Abstract translation: 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

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