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公开(公告)号：US10367511B2
公开(公告)日：2019-07-30
申请号：US16036221
申请日：2018-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun Dusad , Visvesvaraya Pentakota , Mark Baxter Weaver , William Bright , Jiankun Hu
Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
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公开(公告)号：US10185339B2
公开(公告)日：2019-01-22
申请号：US14446815
申请日：2014-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shuaeb Fazeel , Eeshan Miglani , Visvesvaraya Pentakota , Shagun Dusad
Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.
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公开(公告)号：US10050632B2
公开(公告)日：2018-08-14
申请号：US15395489
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun Dusad , Visvesvaraya Pentakota , Mark Baxter Weaver , William Bright , Jiankun Hu
Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
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公开(公告)号：US20180191362A1
公开(公告)日：2018-07-05
申请号：US15909378
申请日：2018-03-01
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
CPC classification number: H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
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公开(公告)号：US09941893B2
公开(公告)日：2018-04-10
申请号：US15485552
申请日：2017-04-12
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
CPC classification number: H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
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Patent Agency Ranking
公开(公告)号：US09847760B1
公开(公告)日：2017-12-19
申请号：US15620171
申请日：2017-06-12
Applicant: Texas Instruments Incorporated
Inventor： Shagun Dusad , Rajendrakumar Joish
CPC classification number: H04B1/40 , G11C27/026 , H03F3/193 , H03F3/45188 , H03F3/505 , H03F2200/451 , H03F2203/45514 , H03F2203/45551 , H03F2203/5024 , H03M1/1245
Abstract: The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.
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公开(公告)号：US20170222658A1
公开(公告)日：2017-08-03
申请号：US15489124
申请日：2017-04-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
CPC classification number: H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
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公开(公告)号：US20150280662A1
公开(公告)日：2015-10-01
申请号：US14637146
申请日：2015-03-03
Applicant: Texas Instruments Incorporated
Inventor： Vajeed Nimran , Raja Sekhar , Sandeep Oswal , Shagun Dusad
CPC classification number: H03F1/56 , G01S7/52033 , H03F3/45475 , H03F2203/45134 , H03F2203/45151 , H03F2203/45528 , H03F2203/45591 , H03G1/0035 , H03G3/3005 , H03G3/301
Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
Abstract translation: 本公开提供了时间增益补偿（TGC）电路。 TGC电路包括阻抗网络。 差分放大器耦合到阻抗网络。 差分放大器包括第一输入端口，第二输入端口，第一输出端口和第二输出端口。 第一反馈电阻耦合在第一输入端口和第一输出端口之间。 第二反馈电阻耦合在第二输入端口和第二输出端口之间。 当TGC电路的增益从最大值变为最小值时，阻抗网络向差分放大器提供固定阻抗。
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公开(公告)号：US20140184330A1
公开(公告)日：2014-07-03
申请号：US13732151
申请日：2012-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun Dusad
IPC: H03G3/00
CPC classification number: H03G3/00 , G01S7/52033 , H03G1/0029 , H03G3/3005
Abstract: In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.
Abstract translation: 在某些实施例中，提供用于时间增益补偿的电路和方法。 电路包括第一运算放大器，其被配置为分别比较从第一和第二输入电路接收的第一和第二输入电压信号，并输出第一运算放大器输出信号。 与第二输入电路的第一半导体元件耦合的控制电路被配置为改变第一半导体元件的第一电阻值以控制第一运算放大器输出信号。 当输入控制电压信号对应于分别与第一运算放大器相关联的第一参考电压和第二参考电压信号时，第一运算放大器输出信号包括相对较高的电压信号和相对低电压信号。 第一运算放大器输出信号被输入到负载半导体元件的栅极端子，以便改变负载半导体元件的阻抗。
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公开(公告)号：US08766721B1
公开(公告)日：2014-07-01
申请号：US13732151
申请日：2012-12-31
Applicant: Texas Instruments Incorporated
Inventor： Shagun Dusad
IPC: H03F3/45
CPC classification number: H03G3/00 , G01S7/52033 , H03G1/0029 , H03G3/3005
Abstract: In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.
Abstract translation: 在某些实施例中，提供用于时间增益补偿的电路和方法。 电路包括第一运算放大器，其被配置为分别比较从第一和第二输入电路接收的第一和第二输入电压信号，并输出第一运算放大器输出信号。 与第二输入电路的第一半导体元件耦合的控制电路被配置为改变第一半导体元件的第一电阻值以控制第一运算放大器输出信号。 当输入控制电压信号对应于分别与第一运算放大器相关联的第一参考电压和第二参考电压信号时，第一运算放大器输出信号包括相对较高的电压信号和相对低电压信号。 第一运算放大器输出信号被输入到负载半导体元件的栅极端子，以便改变负载半导体元件的阻抗。
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