公开(公告)号：US12230595B2

公开(公告)日：2025-02-18

申请号：US17333187

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/488

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

公开(公告)号：US20240371915A1

公开(公告)日：2024-11-07

申请号：US18777699

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L21/311 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US11908818B2

公开(公告)日：2024-02-20

申请号：US17525593

申请日：2021-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2924/13091 ,  H01L2924/13091 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

公开(公告)号：US11894241B2

公开(公告)日：2024-02-06

申请号：US17220339

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chen-Shien Chen ,  Lung-Kai Mao ,  Ming-Da Cheng ,  Wen-Hsiung Lu

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L24/80 ,  H01L2224/80345 ,  H01L2224/80355

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

公开(公告)号：US11848270B2

公开(公告)日：2023-12-19

申请号：US16422988

申请日：2019-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Seng Shue ,  Sheng-Han Tsai ,  Kuo-Chin Chang ,  Mirng-Ji Lii ,  Kuo-Ching Hsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/023 ,  H01L2224/0224 ,  H01L2224/0225 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02235 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/081 ,  H01L2224/0805 ,  H01L2224/08052 ,  H01L2224/08113 ,  H01L2224/16104

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

公开(公告)号：US11532692B2

公开(公告)日：2022-12-20

申请号：US17140766

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L27/08 ,  H01L49/02 ,  H01L21/311 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US20220238353A1

公开(公告)日：2022-07-28

申请号：US17220339

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chen-Shien Chen ,  Lung-Kai Mao ,  Ming-Da Cheng ,  Wen-Hsiung Lu

IPC: H01L21/48 ,  H01L23/498

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

公开(公告)号：US11244919B2

公开(公告)日：2022-02-08

申请号：US16367273

申请日：2019-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

公开(公告)号：US11239305B2

公开(公告)日：2022-02-01

申请号：US16866519

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Yu Wu ,  Mirng-Ji Lii ,  Shang-Yun Tu ,  Ching-Hui Chen

IPC: H01L27/32 ,  H01L51/56

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

公开(公告)号：US20210351076A1

公开(公告)日：2021-11-11

申请号：US17379775

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Mirng-Ji Lii ,  Chien-Hsun Lee ,  Jiun Yi Wu

IPC: H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.