公开(公告)号：US20240387240A1

公开(公告)日：2024-11-21

申请号：US18785410

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US20240347342A1

公开(公告)日：2024-10-17

申请号：US18756008

申请日：2024-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Hung-Yi Huang ,  Yu-Yun Peng ,  Mrunal A. Khaderbad ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Keng-Chu Lin

IPC: H01L21/265 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/26586 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

公开(公告)号：US11972974B2

公开(公告)日：2024-04-30

申请号：US17575444

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li Wang ,  Shuen-Shin Liang ,  Yu-Yun Peng ,  Fang-Wei Lee ,  Chia-Hung Chu ,  Mrunal Abhijith Khaderbad ,  Keng-Chu Lin

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

公开(公告)号：US20240136438A1

公开(公告)日：2024-04-25

申请号：US18395058

申请日：2023-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yun Peng ,  Fu-Ting Yen ,  Ting-Ting Chen ,  Keng-Chu Lin ,  Tsu-Hsiu Perng

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0217 ,  H01L21/02203 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/823468

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

公开(公告)号：US11935752B2

公开(公告)日：2024-03-19

申请号：US17200133

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun Peng ,  Chung-Chi Ko ,  Keng-Chu Lin

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/28158 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/76224

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.

公开(公告)号：US11923367B2

公开(公告)日：2024-03-05

申请号：US17870964

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

公开(公告)号：US11908921B2

公开(公告)日：2024-02-20

申请号：US17412896

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yun Peng ,  Fu-Ting Yen ,  Keng-Chu Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66742 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02167 ,  H01L21/02208 ,  H01L21/02219 ,  H01L21/02326 ,  H01L21/02348 ,  H01L21/31111 ,  H01L29/78696

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

公开(公告)号：US11837544B2

公开(公告)日：2023-12-05

申请号：US17815730

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai Chang ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Chia-Hung Chu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53242

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US20230387017A1

公开(公告)日：2023-11-30

申请号：US18232722

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai Chang ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Chia-Hung Chu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53242

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US11688766B2

公开(公告)日：2023-06-27

申请号：US17712234

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chen-Han Wang ,  Keng-Chu Lin ,  Tetsuji Ueno ,  Ting-Ting Chen

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02447 ,  H01L21/02529 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.