公开(公告)号：US20240260249A1

公开(公告)日：2024-08-01

申请号：US18608199

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US11980016B2

公开(公告)日：2024-05-07

申请号：US17813782

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US11910585B2

公开(公告)日：2024-02-20

申请号：US17873626

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H10B10/00 ,  G06F30/30 ,  G11C11/412

CPC classification number: H10B10/00 ,  G06F30/30 ,  G11C11/412

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

公开(公告)号：US20230354573A1

公开(公告)日：2023-11-02

申请号：US17731781

申请日：2022-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chao-Yuan CHANG ,  Shih-Hao LIN ,  Chia-Hao PAO ,  Feng-Ming CHANG ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC: H01L27/11 ,  G06F30/392 ,  G06F30/398

CPC classification number: H01L27/1116 ,  H01L27/1108 ,  G06F30/392 ,  G06F30/398 ,  G06F30/3953

Abstract: The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.

公开(公告)号：US11791422B2

公开(公告)日：2023-10-17

申请号：US17739802

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/78696 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H10B10/125

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

公开(公告)号：US11728432B2

公开(公告)日：2023-08-15

申请号：US17352587

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76224

Abstract: A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.

公开(公告)号：US11637109B2

公开(公告)日：2023-04-25

申请号：US16915609

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L27/092 ,  H01L21/768 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L21/764

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

公开(公告)号：US11552084B2

公开(公告)日：2023-01-10

申请号：US17248112

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: H01L27/11 ,  G11C11/41 ,  H01L23/528 ,  H01L29/06 ,  G11C11/418 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US11430788B2

公开(公告)日：2022-08-30

申请号：US16798685

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Yi Lin ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

公开(公告)号：US20220262958A1

公开(公告)日：2022-08-18

申请号：US17739802

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.