公开(公告)号：US20190115382A1

公开(公告)日：2019-04-18

申请号：US16218806

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146 ,  H01L31/18

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate having a first photodetector region and forming a gate material over the gate dielectric layer. A dielectric protection layer is deposited over the gate dielectric layer and a first sidewall spacer is formed along a side of the gate material. The dielectric protection layer extends from a first location directly over the first photodetector region to a second location between the first sidewall spacer and the gate dielectric layer.

公开(公告)号：US10164156B2

公开(公告)日：2018-12-25

申请号：US15476370

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Su ,  Hung-Wen Hsu ,  Wei-Chuang Wu ,  Wei-Lin Chen ,  Jiech-Fun Lu

IPC: H01L31/0232 ,  H01L21/00 ,  H01L33/46 ,  H01L27/146 ,  H01L31/056 ,  H01L27/148

Abstract: Structures and formation methods of an image sensor structure are provided. The image sensor structure is provided. The image sensor structure includes a substrate, a photodiode component in the substrate, and a grid structure over the substrate. The grid structure includes a bottom dielectric element over the substrate, a reflective element over the bottom dielectric element, and an upper dielectric element over the reflective element. The reflective element has a sidewall which is anti-corrosive in a basic condition and an acidic condition. The image sensor structure also includes a color filter element over the substrate and surrounded by the grid structure. The color filter element is aligned with the photodiode component.

公开(公告)号：US10163974B2

公开(公告)日：2018-12-25

申请号：US15597452

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.

公开(公告)号：US20180286894A1

公开(公告)日：2018-10-04

申请号：US15471212

申请日：2017-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Han Huang ,  Tzu-Hsiang Chen ,  Shih-Pei Chou ,  Jiech-Fun Lu

IPC: H01L27/146 ,  H01L21/762

Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes an epitaxial layer and a dielectric layer. The epitaxial layer and the dielectric layer are formed in a deep trench of a semiconductor substrate. The epitaxial layer covers a lower portion of sidewall of the trench, and the dielectric layer covers an upper portion of the sidewall of the trench. In the method for fabricating the optical isolation structure, at first, shallow trenches are formed in the semiconductor substrate. Then, the dielectric layer is formed in the shallow trenches. Thereafter, deep trenches are formed passing through the dielectric layers. Then, the epitaxial layer is formed in the deep trenches.

公开(公告)号：US11756970B2

公开(公告)日：2023-09-12

申请号：US17328036

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L27/146 ,  H01L31/0232

CPC classification number: H01L27/14605 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/0232

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprises a plurality of photodetectors disposed within a substrate. A metal grid layer is disposed over the substrate. The metal grid layer comprises a metal grid structure overlying a central pixel region of the substrate. The metal grid layer continuously extends from the central pixel region to a peripheral pixel region of the substrate that laterally encloses the central pixel region. An upper metal structure is disposed over the metal grid layer. The upper metal structure overlies the peripheral pixel region. The upper metal structure is laterally offset from the metal grid structure. A lower surface of the upper metal structure is disposed vertically over an upper surface of the metal grid structure.

公开(公告)号：US11380728B2

公开(公告)日：2022-07-05

申请号：US17022432

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Chung Su ,  Jiech-Fun Lu

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a semiconductor structure. The method includes forming photodetectors within a semiconductor substrate. A charge release layer is deposited over the semiconductor substrate. A conductive contact is formed over the charge release layer such that a contact protrusion of the conductive contact extends through the charge release layer. The charge release layer is disposed along opposing sidewalls of the conductive contact. The charge release layer is electrically coupled to ground via the conductive contact.

公开(公告)号：US11335726B2

公开(公告)日：2022-05-17

申请号：US16804208

申请日：2020-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiech-Fun Lu ,  Chun-Tsung Kuo

IPC: H01L27/146 ,  H04N5/341

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a substrate including a plurality of sidewalls that define a plurality of protrusions along a first side of the substrate. The substrate has a first index of refraction. A photodetector is disposed within the substrate and underlying the plurality of protrusions. A plurality of micro-lenses overlying the first side of the substrate. The micro-lenses have a second index of refraction that is less than the first index of refraction. The micro-lenses are respectively disposed laterally between and directly contact an adjacent pair of protrusions in the plurality of protrusions. Further, the micro-lenses respectively comprise a convex upper surface.

公开(公告)号：US11264469B2

公开(公告)日：2022-03-01

申请号：US16861478

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US11251213B2

公开(公告)日：2022-02-15

申请号：US17063801

申请日：2020-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Huang ,  Jiech-Fun Lu ,  Yu-Chun Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

公开(公告)号：US20210335861A1

公开(公告)日：2021-10-28

申请号：US17017854

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Chun-Tsung Kuo ,  Jiech-Fun Lu ,  Min-Ying Tsai ,  Chiao-Chun Hsu ,  Ching I Li

IPC: H01L27/146

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.