公开(公告)号：US10290635B2

公开(公告)日：2019-05-14

申请号：US15698030

申请日：2017-09-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/768

Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.

公开(公告)号：US20190067446A1

公开(公告)日：2019-02-28

申请号：US15864525

申请日：2018-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Teng-Chun Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/161 ,  H01L27/088

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

公开(公告)号：US20190067445A1

公开(公告)日：2019-02-28

申请号：US15800287

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate; a first semiconductor fin extending upwardly from the substrate; an isolation structure over the substrate and on sidewalls of the first semiconductor fin; a first epitaxial feature over the first semiconductor fin; a dielectric fin partially embedded in the isolation structure and projecting upwardly above the isolation structure; and first and second spacer features over the isolation structure. The first spacer feature is laterally between the first epitaxial feature and the dielectric fin. The first epitaxial feature is laterally between the first and second spacer features. Methods of forming the same are also disclosed.

公开(公告)号：US20190067417A1

公开(公告)日：2019-02-28

申请号：US15689466

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0653 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0886

Abstract: A semiconductor device includes a semiconductor substrate, first and second device fins extending from the semiconductor substrate, and a fill fin disposed on the semiconductor substrate and between the first and second device fins, wherein the fill fin has an opening. The semiconductor device further includes a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.

公开(公告)号：US20180350803A1

公开(公告)日：2018-12-06

申请号：US16045266

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

公开(公告)号：US20180301384A1

公开(公告)日：2018-10-18

申请号：US15485428

申请日：2017-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/84 ,  H01L29/04 ,  H01L27/13 ,  H01L23/00 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823807 ,  H01L27/1207 ,  H01L27/1211 ,  H01L27/13 ,  H01L29/045

Abstract: A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.

公开(公告)号：US10096693B2

公开(公告)日：2018-10-09

申请号：US15896394

申请日：2018-02-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L27/02

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.

公开(公告)号：US20180151688A1

公开(公告)日：2018-05-31

申请号：US15409617

申请日：2017-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US09941279B2

公开(公告)日：2018-04-10

申请号：US15226007

申请日：2016-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/308 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  H01L21/3065

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/108 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.

公开(公告)号：US09911824B2

公开(公告)日：2018-03-06

申请号：US14858862

申请日：2015-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L27/02

CPC classification number: H01L29/6656 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.