公开(公告)号：US20210082803A1

公开(公告)日：2021-03-18

申请号：US16572670

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

公开(公告)号：US12300728B2

公开(公告)日：2025-05-13

申请号：US18581096

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Pei-Yu Wang ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

公开(公告)号：US20240258237A1

公开(公告)日：2024-08-01

申请号：US18633002

申请日：2024-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Yu-Xuan Huang

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

公开(公告)号：US12009293B2

公开(公告)日：2024-06-11

申请号：US17693925

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76877

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

公开(公告)号：US11996293B2

公开(公告)日：2024-05-28

申请号：US17391834

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L21/28123 ,  H01L21/31055 ,  H01L21/32136 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.

公开(公告)号：US20240097001A1

公开(公告)日：2024-03-21

申请号：US18521931

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/458 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

公开(公告)号：US11916128B2

公开(公告)日：2024-02-27

申请号：US18175137

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/0206 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

公开(公告)号：US20230299200A1

公开(公告)日：2023-09-21

申请号：US18324405

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Wei Ju Lee ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L29/7843 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US11764262B2

公开(公告)日：2023-09-19

申请号：US17515674

申请日：2021-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Wei Ju Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes first and second dielectric fins disposed above a substrate, a semiconductor channel layer sandwiched between the first and second dielectric fins, a gate structure engaging the semiconductor channel layer, a source/drain (S/D) feature abutting the semiconductor channel layer and sandwiched between the first and second dielectric fins, and an air gap sandwiched between the first and second dielectric fins. The air gap exposes a first sidewall of the S/D feature facing the first dielectric fin and a second sidewall of the S/D feature facing the second dielectric fin.

公开(公告)号：US20230223459A1

公开(公告)日：2023-07-13

申请号：US18175137

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min Cao ,  Pei-Yu Wang ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L29/513 ,  H01L29/78391 ,  H01L21/0206 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/6684 ,  H01L29/42364 ,  H01L21/823857 ,  H01L29/517

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.