公开(公告)号：US11158644B2

公开(公告)日：2021-10-26

申请号：US16527044

申请日：2019-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hung-Pin Ko

IPC: H01L27/11526 ,  G11C16/08 ,  G11C16/04

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first FET, and a second FET formed over the substrate. The substrate has a first surface and a second surface, and the first surface and the second surface form a step. The first FET comprises a first gate dielectric layer over the first surface of the substrate. The second FET comprises a second gate dielectric layer thinner than the first gate dielectric layer over the second surface of the substrate.

公开(公告)号：US11069625B2

公开(公告)日：2021-07-20

申请号：US16231735

申请日：2018-12-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

Abstract: A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

公开(公告)号：US20210175191A1

公开(公告)日：2021-06-10

申请号：US17181202

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/488 ,  H01L21/768 ,  H01L21/683 ,  H01L25/10

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US20210143131A1

公开(公告)日：2021-05-13

申请号：US17153304

申请日：2021-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tsan Lee ,  Wei-Cheng Wu ,  Tsung-Shu Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

Abstract: An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

公开(公告)号：US20210035953A1

公开(公告)日：2021-02-04

申请号：US17073888

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US20200264231A1

公开(公告)日：2020-08-20

申请号：US16869775

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/00 ,  G01R1/04 ,  G01R31/26

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US10663512B2

公开(公告)日：2020-05-26

申请号：US16232373

申请日：2018-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/00 ,  G01R1/04 ,  G01R31/26

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US10510763B2

公开(公告)日：2019-12-17

申请号：US15607337

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L27/11521 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

公开(公告)号：US20190148389A1

公开(公告)日：2019-05-16

申请号：US16022702

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/40 ,  H01L21/765 ,  H01L23/00

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US20180190345A1

公开(公告)日：2018-07-05

申请号：US15905058

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Min Chan ,  Wei-Cheng Wu ,  Yen-Huei Chen

IPC: G11C11/419 ,  H01L27/06 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0688 ,  H01L27/1104 ,  H01L2224/48227 ,  H01L2224/73265

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.