公开(公告)号：US10957540B2

公开(公告)日：2021-03-23

申请号：US16719311

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L31/102 ,  H01L21/00 ,  H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/306

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US20210074551A1

公开(公告)日：2021-03-11

申请号：US16567290

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC: H01L21/322 ,  H01L23/66 ,  H01L29/06 ,  H01L29/34 ,  H01L21/762

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US10923503B2

公开(公告)日：2021-02-16

申请号：US16024962

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Min-Ying Tsai ,  Alex Usenko

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/331 ,  H01L21/76 ,  H01L21/70 ,  H01L27/12 ,  H01L21/02 ,  H01L29/16 ,  H01L21/762 ,  H01L21/84 ,  H01L29/04 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L31/09

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).

公开(公告)号：US10889097B2

公开(公告)日：2021-01-12

申请号：US16710348

申请日：2019-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chen Tsao ,  Kuo Liang Lu ,  Ru-Liang Lee ,  Sheng-Hsiang Chuang ,  Yu-Hung Cheng ,  Yeur-Luen Tu ,  Cheng-Kang Hu

IPC: B32B38/10 ,  H01L21/67 ,  H01L21/68 ,  H01L21/683

Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.

公开(公告)号：US10658474B2

公开(公告)日：2020-05-19

申请号：US16103101

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US10553474B1

公开(公告)日：2020-02-04

申请号：US16139357

申请日：2018-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L21/762 ,  H01L21/3213

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

公开(公告)号：US20190259655A1

公开(公告)日：2019-08-22

申请号：US16405165

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

公开(公告)号：US10155369B2

公开(公告)日：2018-12-18

申请号：US15613963

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chen Tsao ,  Kuo Liang Lu ,  Ru-Liang Lee ,  Sheng-Hsiang Chuang ,  Yu-Hung Cheng ,  Yeur-Luen Tu ,  Cheng-Kang Hu

IPC: H01L21/30 ,  B32B38/10 ,  H01L21/67 ,  H01L21/68 ,  H01L21/683

Abstract: The present disclosure relates to a method for debonding a pair of bonded substrates. In the method, a debonding apparatus is provided comprising a wafer chuck, a flex wafer assembly, and a set of separating blades. The pair of bonded substrates is placed upon the wafer chuck so that a first substrate of the bonded substrate pair is in contact with a chuck top surface. The flex wafer assembly is placed above the bonded substrate pair so that its first surface is in contact with an upper surface of a second substrate of the bonded substrate pair. A pair of separating blades having different thicknesses is inserted between the first and second substrates from edges of the pair of bonded substrates diametrically opposite to each other while the second substrate is concurrently pulled upward until the flex wafer assembly flexes the second substrate from the first substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.