公开(公告)号：US20250006587A1

公开(公告)日：2025-01-02

申请号：US18341897

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Shu-Yan Jhu

IPC: H01L23/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package with a dummy die having two layers with different thermal conductivities and the method of forming the same are provided. The semiconductor package may include a first semiconductor die, a first bonding layer on the first semiconductor die, a second semiconductor die bonded to the first bonding layer, and a first dummy die bonded to the first bonding layer. The first dummy die may include a substrate, a material layer between the substrate and the first bonding layer, and a second bonding layer between the material layer and the first bonding layer. The material layer may include a first material with a first thermal conductivity and the second bonding layer may include a second material with a second thermal conductivity different from the first thermal conductivity.

公开(公告)号：US20240404991A1

公开(公告)日：2024-12-05

申请号：US18328430

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Min-Chien Hsiao ,  Kuo-Chiang Ting ,  Yen-Ming Chen ,  Ashish Kumar Sahoo ,  Chen-Sheng Lin ,  Hsin-Yu Pan

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments include methods of forming three-dimensional packages and the packages resulting therefrom. The packages may utilize a bridge die to electrically connect one die to another die and at least one additional die adjacent to the bridge die. The height-to-width ratio of the gap between the bridge die and the at least one additional die is controlled by thinning the bridge die to be thinner than the at least one additional die. The packages may utilize landing structures to adjoin a dielectric material of an attached die to a metallic landing structure of a base die.

公开(公告)号：US12135454B2

公开(公告)日：2024-11-05

申请号：US17232567

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting

IPC: G02B6/122 ,  G02B6/12

Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein. A method includes providing a first material layer between a second material layer and a semiconductor substrate and forming a first waveguide in the second material layer. The method also includes forming a photonic die over the first waveguide and forming a first cavity in the semiconductor substrate and exposing the first layer. Once formed, the first cavity is filled with a first backfill material adjacent the first layer. The methods also include electrically coupling an electronic die to the photonic die. Some methods include packaging the semiconductor device in a packaged assembly.

公开(公告)号：US20240266303A1

公开(公告)日：2024-08-08

申请号：US18635315

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Hsien-Pin Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

公开(公告)号：US20240213236A1

公开(公告)日：2024-06-27

申请号：US18151629

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yan Jhu ,  Kuo-Chiang Ting ,  Sung-Feng Yeh

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L23/36 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/29186 ,  H01L2224/32245 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device includes a first semiconductor package comprising: a first interconnect structure on a first semiconductor substrate; through substrate vias electrically coupled to the first interconnect structure extending through the first semiconductor substrate; and a second semiconductor package directly bonded to the first semiconductor package, the second semiconductor package comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate. The semiconductor device further includes a silicon layer on a surface of the second semiconductor package that is opposite to the first semiconductor package; and a heat dissipation structure attached to the silicon layer.

公开(公告)号：US11980015B2

公开(公告)日：2024-05-07

申请号：US17883910

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/417 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L49/02 ,  H03K19/20 ,  H10B43/27

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/417 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L28/00 ,  H03K19/20 ,  H10B10/18 ,  H10B43/27

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US20230384517A1

公开(公告)日：2023-11-30

申请号：US18366758

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/1225 ,  G02B6/12019 ,  G02B2006/12173 ,  G02B2006/12176 ,  G02B2006/1213

Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein. A method includes providing a first material layer between a second material layer and a semiconductor substrate and forming a first waveguide in the second material layer. The method also includes forming a photonic die over the first waveguide and forming a first cavity in the semiconductor substrate and exposing the first layer. Once formed, the first cavity is filled with a first backfill material adjacent the first layer. The methods also include electrically coupling an electronic die to the photonic die. Some methods include packaging the semiconductor device in a packaged assembly.

公开(公告)号：US11747563B2

公开(公告)日：2023-09-05

申请号：US17818845

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/124

CPC classification number: G02B6/13 ,  G02B6/12002 ,  G02B6/124 ,  G02B2006/12107

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

公开(公告)号：US20230014813A1

公开(公告)日：2023-01-19

申请号：US17952681

申请日：2022-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US20220334310A1

公开(公告)日：2022-10-20

申请号：US17232567

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting

IPC: G02B6/122 ,  G02B6/12

Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein. A method includes providing a first material layer between a second material layer and a semiconductor substrate and forming a first waveguide in the second material layer. The method also includes forming a photonic die over the first waveguide and forming a first cavity in the semiconductor substrate and exposing the first layer. Once formed, the first cavity is filled with a first backfill material adjacent the first layer. The methods also include electrically coupling an electronic die to the photonic die. Some methods include packaging the semiconductor device in a packaged assembly.