-
公开(公告)号：US20190385672A1
公开(公告)日：2019-12-19
申请号：US16415554
申请日：2019-05-17
IPC分类号： G11C11/419 , G11C11/418
摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
-
52.发明授权公开(公告)号：US10268787B2
公开(公告)日：2019-04-23
申请号：US15651714
申请日：2017-07-17
IPC分类号： G06F17/50
摘要： A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.
-
公开(公告)号：US09959916B2
公开(公告)日：2018-05-01
申请号：US15589313
申请日：2017-05-08
IPC分类号： G11C7/00 , G11C7/12 , G11C5/14 , G11C7/10 , G11C7/06 , G11C7/22 , G11C8/10 , G11C8/06 , G11C8/08 , G11C11/418 , G11C11/417
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/065 , G11C7/10 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/417 , G11C11/418
摘要： A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.
-
公开(公告)号：US09824729B2
公开(公告)日：2017-11-21
申请号：US15434541
申请日：2017-02-16
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
CPC分类号： G11C7/12 , G11C7/227 , G11C11/419
摘要： A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.
-
公开(公告)号：US09685224B2
公开(公告)日：2017-06-20
申请号：US14713648
申请日：2015-05-15
发明人： Chen-Lin Yang , Cheng Hung Lee , Hung-Jen Liao , Kao-Cheng Lin , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC分类号： G11C5/14 , G11C11/417 , G11C7/12
CPC分类号： G11C11/417 , G11C5/148 , G11C7/12
摘要： A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.
-
公开(公告)号：US09281056B2
公开(公告)日：2016-03-08
申请号：US14308065
申请日：2014-06-18
发明人： Wei-Cheng Wu , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Ping-Wei Wang
IPC分类号： G11C11/00 , G11C11/419 , G11C11/4063 , G11C11/409
CPC分类号： G11C11/419 , G11C11/4063 , G11C11/409 , G11C11/412
摘要： A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors.
摘要翻译： 一种包括位单元的静态随机存取存储器（SRAM），其中所述位单元包括至少两个p型通道门。 SRAM还包括连接到位单元的位线和连接到位单元的位线条。 SRAM还包括连接到位线和位线条的预放电电路，其中预放电电路包括至少两个n型晶体管。 SRAM还包括连接到位线和位线条的交叉耦合晶体管，其中交叉耦合晶体管的每个晶体管是n型晶体管。 SRAM还包括连接到位线和位线条的写入多路复用器，其中写入多路复用器包括两个p型晶体管。
-
公开(公告)号：US09257172B2
公开(公告)日：2016-02-09
申请号：US14193456
申请日：2014-02-28
发明人： Hidehiro Fujiwara , Kao-Cheng Lin , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C7/10 , G11C11/419 , G11C5/02 , G11C5/06 , G11C7/22
CPC分类号： G11C11/419 , G11C5/02 , G11C5/06 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/22 , G11C8/14 , G11C8/16 , G11C11/417 , H01L23/535 , H01L27/1104
摘要： A circuit includes a first data line, a second data line, a reference node, and a memory cell. The reference node is configured to have a reference voltage level corresponding to a first logical value. The memory cell includes a data node, a first transistor and a second transistor connected in series between the first data line and the reference node, and a third transistor between the data node and the second data line. A gate of the first transistor is coupled to the data node, and the first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.
摘要翻译： 电路包括第一数据线，第二数据线，参考节点和存储器单元。 参考节点被配置为具有对应于第一逻辑值的参考电压电平。 存储单元包括串联连接在第一数据线和参考节点之间的数据节点，第一晶体管和第二晶体管，以及数据节点和第二数据线之间的第三晶体管。 第一晶体管的栅极耦合到数据节点，并且第一晶体管被配置为当第一晶体管的栅极具有对应于第一逻辑值的电压电平时截止。 当第三晶体管的栅极具有与不同于第一逻辑值的第二逻辑值相对应的电压电平时，第三晶体管被配置为截止。
-
公开(公告)号：US20240185911A1
公开(公告)日：2024-06-06
申请号：US18443979
申请日：2024-02-16
发明人： Yi-Tzu Chen , Ching-Wei Wu , Hau-Tai Shieh , Hung-Jen Liao
IPC分类号： G11C11/408 , G11C5/02 , G11C5/06 , G11C11/4093
CPC分类号： G11C11/4085 , G11C5/025 , G11C5/06 , G11C11/4093
摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
-
公开(公告)号：US11854943B2
公开(公告)日：2023-12-26
申请号：US18153475
申请日：2023-01-12
发明人： Hidehiro Fujiwara , Tze-Chiang Huang , Hong-Chen Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： G11C16/04 , H01L23/48 , H10B10/00 , G11C11/418 , H01L21/768
CPC分类号： H01L23/481 , G11C11/418 , H01L21/76898 , H10B10/18
摘要： An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.
-
公开(公告)号：US20230267989A1
公开(公告)日：2023-08-24
申请号：US18306762
申请日：2023-04-25
发明人： Yi-Tzu Chen , Ching-Wei Wu , Hau-Tai Shieh , Hung-Jen Liao
IPC分类号： G11C11/408 , G11C5/02 , G11C5/06 , G11C11/4093
CPC分类号： G11C11/4085 , G11C5/025 , G11C5/06 , G11C11/4093
摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
-
-
-
-
-
-
-
-
-
搜索结果
110 条记录 (耗时 0.03 秒)
