公开(公告)号：US06972996B2

公开(公告)日：2005-12-06

申请号：US10922950

申请日：2004-08-23

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

IPC分类号： H01L21/8247 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.

公开(公告)号：US20050213402A1

公开(公告)日：2005-09-29

申请号：US11134576

申请日：2005-05-19

申请人： Koichi Kawai ,  Kenichi Imamiya

发明人： Koichi Kawai ,  Kenichi Imamiya

IPC分类号： G01R31/28 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/26

CPC分类号： G11C29/025 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/02 ,  G11C29/26

摘要： A semiconductor memory device vice disclosed herein comprises: a memory cell array divided into a plurality of blocks, each of which includes a plurality of memory cells; a plurality of row decoders which correspond to the blocks, each of the row decoders including an access information holder configured to hold access information indicating whether its corresponding row decoder has been accessed; and an access information reader configured to read the access information held in the access information holders.

摘要翻译： 本文公开的半导体存储器件副本包括：分成多个块的存储单元阵列，每个块包括多个存储单元; 对应于所述块的多个行解码器，每个行解码器包括访问信息保持器，其被配置为保存指示其对应的行解码器是否已被访问的访问信息; 以及访问信息读取器，被配置为读取保持在访问信息保持器中的访问信息。

公开(公告)号：US06930954B2

公开(公告)日：2005-08-16

申请号：US10822957

申请日：2004-04-13

申请人： Kenichi Imamiya ,  Koichi Kawai

发明人： Kenichi Imamiya ,  Koichi Kawai

IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C7/20 ,  G11C11/00 ,  G11C16/06 ,  G11C16/20 ,  G11C16/32 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C7/20 ,  G11C16/20 ,  G11C16/32 ,  G11C29/70

摘要： A non-volatile semiconductor memory device includes a memory cell array having electrically erasable and programmable non-volatile memory cells, a part of the memory cell array being defined as a initial set-up data region for storing a plurality of initial set-up data that define memory operation conditions, data latch circuits for holding the initial set-up data read out from the initial set-up data region, a controller for controlling data program and erase operations for the memory cell array, and a clock generator for generating a clock signal that is used to define an operation timing of the controller, wherein the controller is configured to perform such an initial set-up operation that sequentially reads out the plurality of initial set-up data stored in the initial set-up data region and transfers them to the respective data latch circuits on receipt of power-on or a command input, the initial set-up operation being so performed as to read out a clock cycle adjustment data within the plurality of initial set-up data stored in the initial set-up data region in the beginning, thereby adjusting a clock cycle of the clock signal output from the clock generator by use of the clock cycle adjustment data, and then reads out the remaining initial set-up data by use of the adjusted clock signal.

摘要翻译： 非易失性半导体存储器件包括具有电可擦除可编程非易失性存储器单元的存储单元阵列，存储单元阵列的一部分被定义为用于存储多个初始设置数据的初始设置数据区域 定义存储器操作条件的数据锁存电路，用于保持从初始设置数据区读出的初始设置数据的数据锁存电路，用于控制存储器单元阵列的数据编程和擦除操作的控制器，以及用于产生 用于定义控制器的操作定时的时钟信号，其中控制器被配置为执行这样的初始建立操作，其顺序地读出存储在初始设置数据区域中的多个初始建立数据，以及 在接收到电源接通或命令输入时将它们传送到相应的数据锁存电路，初始设置操作被执行以读出时钟周期调整数据 在开始时存储在初始设置数据区域中的多个初始设置数据，从而通过使用时钟周期调整数据来调整从时钟发生器输出的时钟信号的时钟周期，然后读出 剩余的初始设置数据通过使用调整后的时钟信号。

公开(公告)号：US06912157B2

公开(公告)日：2005-06-28

申请号：US10607153

申请日：2003-06-27

申请人： Hiroshi Nakamura ,  Kenichi Imamiya

发明人： Hiroshi Nakamura ,  Kenichi Imamiya

IPC分类号： G11C11/413 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  H01L27/115

CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459 ,  H01L27/115

摘要： A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

公开(公告)号：US20050063209A1

公开(公告)日：2005-03-24

申请号：US10957722

申请日：2004-10-05

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00 ,  G11C5/06

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. By use of the semiconductor memory device, occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array can be prevented, and the manufacturing yield can be made high and the operation reliability can be made high without substantially increasing the chip size.

摘要翻译： 提供一种半导体存储器件，其能够防止由于存储单元阵列的端部区域中的蚀刻精度降低而导致的缺陷的发生，并且实现了具有高操作可靠性和高制造成品率的便宜的芯片。 第一块由具有连接的多个存储单元的第一存储单元单元构成，第二块由具有连接的多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块 在其两端部分，并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。 通过使用半导体存储器件，可以防止由存储单元阵列的端部区域中的蚀刻精度降低引起的缺陷的发生，并且可以使制造成品率高，并且可以使操作可靠性高而无需高 大大增加芯片尺寸。

公开(公告)号：US06865112B2

公开(公告)日：2005-03-08

申请号：US10795881

申请日：2004-03-08

申请人： Koichi Kawai ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Koji Hosono

发明人： Koichi Kawai ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Koji Hosono

IPC分类号： G11C16/02 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3454

摘要： A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

摘要翻译： 提供多个存储单元阵列。 每个存储单元阵列具有多个存储单元，并且存储单元连接到多个字线。 对应于多个存储单元阵列，提供多个字线驱动电路和多个位线控制电路。 每个字线驱动电路选择并驱动相应存储单元阵列的字线。 每个位控制电路对预先写在相应的存储单元阵列的多个存储单元中的数据进行验证读取，并且基于一个对应的字线驱动电路的字线控制选择和驱动操作 结果验证阅读。

公开(公告)号：US20050018462A1

公开(公告)日：2005-01-27

申请号：US10922950

申请日：2004-08-23

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

IPC分类号： H01L21/8247 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C19/08

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.

摘要翻译： 半导体器件包括存储单元阵列和字线选择电路。 存储单元阵列包括以行和列排列的多个存储单元。 存储单元阵列包括其中每个存储单元被布置的多个块。 字线选择电路包括以列和列方向布置的传输晶体管，并且被配置为通过传输晶体管的电流路径将多个不同的电压传送到字线，并且选择所述多个块的至少一行的存储单元 。 转移晶体管包括第一组，其在写入操作中传送施加到字线的最低电压电压，第二组被布置为不与第一组相邻，并且传送施加到第一组的最高电压电压 写字操作中的字线。

公开(公告)号：US20050001306A1

公开(公告)日：2005-01-06

申请号：US10902291

申请日：2004-07-30

申请人： Mie Matsuo ,  Kenichi Imamiya

发明人： Mie Matsuo ,  Kenichi Imamiya

IPC分类号： G11C16/02 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2224/16145 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596

摘要： Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

摘要翻译： 公开了一种具有多个半导体集成电路芯片堆叠的叠层型半导体器件，每个半导体集成电路芯片包括保持电路，该保持电路保持电子写入芯片中的关于芯片的识别信息，设置识别信息的识别信息设置电路 关于芯片，在多个半导体集成电路芯片已被堆叠之后的保持电路中，以及至少一个设置终端，用于在保持电路中设置关于芯片的识别信息，其中至少一个设置终端 半导体集成电路芯片连接到任何其它半导体集成电路芯片的至少一个相应的设置端子。

公开(公告)号：US06791175B2

公开(公告)日：2004-09-14

申请号：US10255960

申请日：2002-09-27

申请人： Mie Matsuo ,  Kenichi Imamiya

发明人： Mie Matsuo ,  Kenichi Imamiya

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2224/16145 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596

摘要： Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

摘要翻译： 公开了一种具有多个半导体集成电路芯片堆叠的叠层型半导体器件，每个半导体集成电路芯片包括保持电路，该保持电路保持电子写入芯片中的关于芯片的识别信息，设置识别信息的识别信息设置电路 关于芯片，在多个半导体集成电路芯片已被堆叠之后的保持电路中，以及至少一个设置终端，用于在保持电路中设置关于芯片的识别信息，其中至少一个设置终端 半导体集成电路芯片连接到任何其它半导体集成电路芯片的至少一个相应的设置端子。

公开(公告)号：US06760256B2

公开(公告)日：2004-07-06

申请号：US10302771

申请日：2002-11-21

申请人： Kenichi Imamiya

发明人： Kenichi Imamiya

IPC分类号： G11C1604

CPC分类号： G06F9/4403 ,  G06F9/24 ,  G11C16/20

摘要： A non-volatile semiconductor memory device includes a non-volatile memory element group having a first storage area which stores booting data and a second storage area to store storage addresses of the first storage area. The device further includes a detecting circuit which detects turn-ON of a power supply. The device further includes a register to which the storage address stored in the second storage area is read out and transferred from the non-volatile memory element group when the detecting circuit detects turn-ON of the power supply, and a control circuit which performs a control operation to output booting data stored in the first storage area and corresponding to the storage address transferred to the register after an initialization operation performed at the power supply turn-ON time is terminated.