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    Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
    52.
    发明授权
    Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization 失效
    使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度

    公开(公告)号：US6107653A

    公开(公告)日：2000-08-22

    申请号：US103672

    申请日：1998-06-23

    申请人： Eugene A. Fitzgerald

    发明人： Eugene A. Fitzgerald

    IPC分类号： H01L21/20 ,  H01L31/0256

    CPC分类号： H01L21/02505 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  Y10S438/933

    摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer oil the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

    摘要翻译： 一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，所述第一层具有被平坦化的表面，并且至少一个第二晶体外延层对所述至少一个第一层进行油化。 在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。 在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变， 所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。 在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。

    Monolithically integrated semiconductor materials and devices
    57.
    发明授权
    Monolithically integrated semiconductor materials and devices 有权
    单片集成半导体材料和器件

    公开(公告)号：US08012592B2

    公开(公告)日：2011-09-06

    申请号：US11591333

    申请日：2006-11-01

    申请人： Eugene A. Fitzgerald

    发明人： Eugene A. Fitzgerald

    IPC分类号： B32B9/04 ,  B32B13/04 ,  B32B9/00 ,  B32B19/00 ,  H01L29/66 ,  H01L21/02

    CPC分类号： H01L27/14601 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/76254 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/144 ,  H01L27/1446 ,  H01L27/14683 ,  H01L27/15 ,  H01L27/156 ,  H01L31/0328 ,  H01L31/143 ,  H01L31/162 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

    摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The semiconductor structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region, a monocrystalline silicon layer disposed over the insulating layer in the first region, and a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region. The second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon.

    摘要翻译： 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。 在一种结构中，半导体结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。 半导体结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层，设置在第一区域中的绝缘层上的单晶硅层和设置在第一单晶的至少一部分上的第二单晶半导体层 半导体层在第二区域中并且不存在于第一区域中。 第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。

    Strained tri-channel layer for semiconductor-based electronic devices
    59.
    发明授权
    Strained tri-channel layer for semiconductor-based electronic devices 有权
    用于基于半导体的电子器件的应变三沟道层

    公开(公告)号：US07791107B2

    公开(公告)日：2010-09-07

    申请号：US10869463

    申请日：2004-06-16

    申请人： Saurabh Gupta ,  Minjoo Larry Lee ,  Eugene A. Fitzgerald

    发明人： Saurabh Gupta ,  Minjoo Larry Lee ,  Eugene A. Fitzgerald

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966

    摘要： A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.

    摘要翻译： 基于半导体的结构包括衬底层，与衬底层相邻的压缩应变半导体层以提供用于部件的沟道，以及布置在衬底层和压缩应变半导体层之间的拉伸应变半导体层。 一种制造电子器件的方法包括在应变诱导基片上提供第一拉伸应变层，在第一拉伸应变层上形成压缩应变层，以及在压缩应变层上形成第二拉伸应变层。 第一和第二拉伸应变层可以由硅形成，并且压缩应变层可以由硅和锗形成。

    Methods of fabricating dual layer semiconductor devices
    60.
    发明授权
    Methods of fabricating dual layer semiconductor devices 有权
    制造双层半导体器件的方法

    公开(公告)号：US07465619B2

    公开(公告)日：2008-12-16

    申请号：US11130575

    申请日：2005-05-17

    申请人： Eugene A. Fitzgerald

    发明人： Eugene A. Fitzgerald

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/1054 ,  Y10S438/933

    摘要： A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.

    摘要翻译： 基于半导体的器件包括沟道层，其包括远端层和与远端层接触的近端层。 远端层支撑至少一个p沟道分量的至少一部分空穴传导，并且近端支撑至少一个n沟道分量的至少一部分电子传导。 近端层具有允许空穴波函数从近端层有效地延伸到远侧层中的厚度，以便于远端层的空穴传导。 一种用于制造基于半导体的器件的方法包括提供沟道层的远端部分并提供沟道层的近端部分。