公开(公告)号：US06673664B2

公开(公告)日：2004-01-06

申请号：US09978487

申请日：2001-10-16

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

IPC分类号： H01L218238

CPC分类号： H01L29/51 ,  H01L21/28291 ,  H01L21/31691 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/516

摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.

摘要翻译： 制造自对准铁电存储晶体管的方法包括制备衬底，浅沟槽隔离，n多晶硅; 以及形成栅叠层，包括：沉积氮化硅层; 选择性地蚀刻氮化硅，底部电极和多晶硅; 选择性地将多晶硅蚀刻到第一介电层的水平面; 以及植入和激活离子以形成源区和漏区; 形成侧壁阻挡层; 沉积一层铁电材料; 在铁电材料上形成顶部电极结构; 并完成结构，包括钝化，氧化物沉积和金属化。

公开(公告)号：US06616857B2

公开(公告)日：2003-09-09

申请号：US09942203

申请日：2001-08-29

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01B108

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US06475813B1

公开(公告)日：2002-11-05

申请号：US09929711

申请日：2001-08-13

申请人： Tingkai Li ,  Wei Pan ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Pan ,  Sheng Teng Hsu

IPC分类号： A01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  C30B25/02 ,  C30B29/30 ,  C30B29/32 ,  H01L21/31604

摘要： A method of fabricating a c-axis ferroelectric thin film includes preparing a substrate; depositing a layer of ferroelectric material by metal organic chemical vapor deposition, including using a precursor solution having a ferroelectric material concentration of about 0.1 M/L at a vaporizer temperature of between about 140° C. to 200° C.; and annealing the substrate and the ferroelectric material at a temperature between about 500° C. to 560° C. for between about 30 minutes to 120 minutes.

摘要翻译： 制造c轴铁电薄膜的方法包括：制备基板; 通过金属有机化学气相沉积沉积铁电材料层，包括在蒸发器温度为约140℃至200℃之间使用铁电材料浓度为约0.1M / L的前体溶液; 以及在大约500℃至560℃之间的温度下将所述衬底和所述铁电材料退火约30分钟至120分钟。

公开(公告)号：US06440752B1

公开(公告)日：2002-08-27

申请号：US09817712

申请日：2001-03-26

申请人： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01G706

CPC分类号： H01L28/75 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/55

摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.

摘要翻译： 用于铁电体器件的电极包括底部电极; 铁电层; 以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。 在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

公开(公告)号：US06410343B1

公开(公告)日：2002-06-25

申请号：US09301420

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US6048740A

公开(公告)日：2000-04-11

申请号：US187238

申请日：1998-11-05

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。 铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ，其中Δ是光刻工艺的对准公差。

公开(公告)号：US07514282B2

公开(公告)日：2009-04-07

申请号：US11649634

申请日：2007-01-04

申请人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/306 ,  H01L29/0669 ,  H01L29/0673 ,  Y10S977/743

摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

摘要翻译： 亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒阵列，在二氧化硅棒周围形成Si 3 N 4管。 二氧化硅棒被蚀刻掉。 然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4管下面的Si管。 最后，去除Si3N4管。

公开(公告)号：US20080315255A1

公开(公告)日：2008-12-25

申请号：US12199144

申请日：2008-08-27

申请人： Jer-Shen Maa ,  Tingkai Li ,  Douglas J. Tweet ,  Gregory M. Stecker ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Tingkai Li ,  Douglas J. Tweet ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC分类号： H01L29/267

CPC分类号： H01L29/267 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02656 ,  H01L29/045 ,  H01L29/2003

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供具有第一热膨胀系数（TEC）的（111）Si衬底，并且形成覆盖Si衬底的硅 - 锗（SiGe）膜。 沉积SiGe膜上的缓冲层。 缓冲层可以是氮化铝（AlN）或铝 - 氮化镓（AlGaN）。 沉积GaN缓冲层，其具有大于第一TEC的第二TEC。 SiGe电影拥有第三个TEC，其值在第一和第二TEC之间。 一方面，可以形成具有Ge含量比在约0％至50％的范围内的等级SiGe膜，其中Ge含量随着梯度SiGe膜厚度而增加。

公开(公告)号：US07407858B2

公开(公告)日：2008-08-05

申请号：US11403020

申请日：2006-04-11

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/336 ,  H01L31/072

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1641

摘要： A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.

摘要翻译： 制造RRAM的方法包括制备衬底并形成底部电极或衬底。 使用MOCVD或液体MOCVD将PCMO层沉积在底部电极上，随后进行后退火处理。 沉积的PCMO薄膜具有结晶的PCMO结构或纳米尺寸和无定形PCMO结构。 顶部电极形成在PCMO层上。

公开(公告)号：US20080050872A1

公开(公告)日：2008-02-28

申请号：US11510428

申请日：2006-08-24

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/8244 ,  H01L21/8234

CPC分类号： H01L27/101 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/147

摘要： A method of selecting a cathode material and a resistance material for use in a RRAM includes determining the work function of a group of potential resistance materials; determining the work function of a group of potential cathode materials; and selecting a suitable material for the resistance material from the group of potential resistance materials and selecting a suitable material for the cathode material from the group of potential cathode material, wherein the work function of the cathode material is at least 0.2 eV less than the work function of the resistance material.

摘要翻译： 选择用于RRAM的阴极材料和电阻材料的方法包括确定一组电阻材料的功函数; 确定一组潜在阴极材料的功函数; 并从潜在的电阻材料组中选择合适的电阻材料材料，并从潜在的阴极材料组中选择合适的阴极材料材料，其中阴极材料的功函数比工件小至少0.2eV 电阻材料的功能。