公开(公告)号：US07403415B2

公开(公告)日：2008-07-22

申请号：US11698872

申请日：2007-01-29

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2 )≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1 /L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US20070139999A1

公开(公告)日：2007-06-21

申请号：US11698872

申请日：2007-01-29

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (1/3)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

公开(公告)号：US06897523B2

公开(公告)日：2005-05-24

申请号：US10211705

申请日：2002-08-05

申请人： Shuichi Ueno ,  Haruo Furuta ,  Shigehiro Kuge ,  Hiroshi Kato

发明人： Shuichi Ueno ,  Haruo Furuta ,  Shigehiro Kuge ,  Hiroshi Kato

IPC分类号： H01L29/78 ,  H01L29/792 ,  H01L29/861 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/8616

摘要： A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons: 8a) are trapped on the drain region (2) side of a silicon nitride film (4b) sandwiched between films of silicon oxide (4a, 4c). When a bias voltage is applied between the drain and source with the negatively charged particles (8a) thus trapped and in-channel charged particles (9a) induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.

摘要翻译： 提供一种半导体器件，其包括由MISFET形成的二极管，其具有接近于理想二极管的电流 - 电压特性。 负电粒子（例如电子：8a）被捕获在夹在氧化硅（4a，4c）的膜之间的氮化硅膜（4b）的漏极区（2）侧上。 当在漏极和源极之间施加偏置电压时，带负电荷的颗粒（8a）被这样捕获并且由它们引起的通道内带电粒子（9a），MISFET对通道形成具有不同的阈值，取决于它是否是 正向偏压或反向偏压。 也就是说，当施加反向偏压时，沟道形成不充分，并且源极 - 漏极电流不太可能流动，而沟道形成充分，并且当施加正向偏压时流过大的源极 - 漏极电流。 这提供了接近理想二极管的电流电压特性。

公开(公告)号：US06815295B1

公开(公告)日：2004-11-09

申请号：US09429283

申请日：1999-10-28

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L21335

CPC分类号： H01L27/11526 ,  H01L21/76218 ,  H01L21/8234 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.

摘要翻译： 在根据本发明的半导体器件及其制造方法中，消除了阈值与扩散层泄漏之间的折衷关系，并且不需要在多于一个阶段形成栅极氧化膜。 由于在N沟道型MOS晶体管（T41〜T43）的栅电极（4A〜4C）之间氮的浓度彼此不同，因此导入氮区域（N1〜N3）的氮浓度因此不同 。 栅电极中的氮浓度按预期的较高阈值的顺序逐渐降低。

公开(公告)号：US06770522B2

公开(公告)日：2004-08-03

申请号：US10444959

申请日：2003-05-27

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052

摘要： A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electric characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug. An insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film can be made small in a MOS transistor for a memory cell part, and a forming width of a sidewall insulating film can be made large in a MOS transistor for a high voltage circuit part. Thereupon, in the high voltage circuit part, a source/drain active layer can be formed in the position more distant from a gate electrode.

摘要翻译： 一种半导体器件及其制造方法，其适用于在一个半导体基板上形成用于存储单元的晶体管和高电压电路部分的晶体管，此外，在侧壁 提供了共享接触插塞部件中的绝缘膜。 通过在共享接触插塞的形成部分中去除侧壁绝缘膜的部分上执行附加杂质注入来形成有源层。 在高压电路部分层叠绝缘膜，形成宽幅的侧壁绝缘膜。 因此，可以在用于存储单元部分的MOS晶体管中使侧壁绝缘膜的形成宽度小，并且在用于高电压电路部分的MOS晶体管中可以使侧壁绝缘膜的形成宽度大。 因此，在高电压电路部分中，可以在远离栅电极的位置形成源极/漏极有源层。

公开(公告)号：US06521527B1

公开(公告)日：2003-02-18

申请号：US09922663

申请日：2001-08-07

申请人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

发明人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

IPC分类号： H01L2144

CPC分类号： H01L29/0847 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66765 ,  H01L29/7833 ,  H01L29/78618

摘要： Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

摘要翻译： 获得的是能够防止栅电极中所含杂质扩散的半导体器件及其制造方法。 在该半导体器件中，形成在P型硅衬底上的栅极氧化膜和P +型栅极掺杂有氮。

公开(公告)号：US06255146B1

公开(公告)日：2001-07-03

申请号：US09699461

申请日：2000-10-31

申请人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

发明人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC分类号： H01L2100

CPC分类号： H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

摘要： According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

摘要翻译： 根据制造薄膜晶体管（TFT）的方法，通过将硅或氮离子注入到多晶硅的区域中形成非晶硅，而位于栅电极的侧壁的区域选择性地使用步骤部分 栅电极。 然后，进行热处理以将非晶硅转化为多晶硅，剩余的多晶硅作为晶种。 结果，可以均匀地形成具有大晶粒尺寸的晶粒的多晶硅。 因此，可以提高TFT的电特性，并且每个TFT之间的电特性没有差异。

公开(公告)号：US06188085B1

公开(公告)日：2001-02-13

申请号：US09335691

申请日：1999-06-18

申请人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

发明人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC分类号： H01L29786

CPC分类号： H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

摘要： According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

公开(公告)号：US6153910A

公开(公告)日：2000-11-28

申请号：US940400

申请日：1997-10-01

申请人： Hidekazu Oda ,  Shuichi Ueno ,  Takehisa Yamaguchi

发明人： Hidekazu Oda ,  Shuichi Ueno ,  Takehisa Yamaguchi

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/772 ,  H01L29/76

CPC分类号： H01L21/26506 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/66575

摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

摘要翻译： 在硅衬底的表面上形成硼扩散区。 在硼扩散区的表面形成一对n型源/漏区。 在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。 在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。 氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。 由此，可以获得容易小型化的晶体管结构。

公开(公告)号：US6020610A

公开(公告)日：2000-02-01

申请号：US946659

申请日：1997-10-07

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： With a semiconductor device and according to a manufacturing method of the invention, a trade-off relationship between a threshold value and a diffusion layer leak is eliminated, and it is not necessary to form a gate oxide film at a plurality of steps. Gate electrodes (4A, 4B and 4C) respectively comprise a polysilicon layer (M1) and a WSi layer (L1), the polysilicon layer (M1) and a WSi layer (L2), the polysilicon layer (M1) and a WSi layer (L3), which are respectively stacked in this order on a gate oxide film (3). Channel dope layers (103A, 103B and 103C) are formed within a well layer (101) respectively under the gate electrodes (4A, 4B and 4C).

摘要翻译： 利用半导体器件并且根据本发明的制造方法，消除了阈值和扩散层泄漏之间的权衡关系，并且不需要在多个步骤形成栅极氧化膜。 栅极（4A，4B和4C）分别包括多晶硅层（M1）和WSi层（L1），多晶硅层（M1）和WSi层（L2），多晶硅层（M1）和WSi层 L3），它们分别按栅极氧化膜（3）层叠。 通道掺杂层（103A，103B和103C）分别在栅电极（4A，4B和4C）的阱层（101）内形成。