Optical mask and MOPA laser apparatus including the same
    51.
    发明申请
    Optical mask and MOPA laser apparatus including the same 失效
    光学掩模和包括其的MOPA激光装置

    公开(公告)号:US20050111514A1

    公开(公告)日:2005-05-26

    申请号:US10992218

    申请日:2004-11-19

    摘要: The present invention relates to an optical mask at low cost and so on having a structure capable of reducing further a peak of beam intensity caused by diffraction. The optical mask is constructed by overlapping a first mask and a second mask. The first mask and second mask each are a serrated aperture mask. The schematic shapes of the respective apertures of the first mask and second mask are almost rectangular and identical to each other. The fringe defining the aperture of the first mask is machined in a serrated shape, and the fringe defining the aperture of the second mask also is machined in a serrated shape. In the optical mask, the first mask and second mask are overlapped so that the serrations of the fringes defining the respective apertures of the first mask and second mask are located alternately.

    摘要翻译: 本发明涉及一种低成本的光掩模,具有能够进一步降低由衍射引起的束强度的峰值的结构。 光掩模通过重叠第一掩模和第二掩模构成。 第一掩模和第二掩模各自是锯齿状孔径掩模。 第一掩模和第二掩模的相应孔的示意形状几乎是矩形的并且彼此相同。 限定第一掩模的孔径的边缘被加工成锯齿状,并且限定第二掩模的孔口的边缘也被加工成锯齿状。 在光学掩模中,第一掩模和第二掩模重叠,使得限定第一掩模和第二掩模的各个孔的条纹的锯齿交替地定位。

    Spray distribution measuring device and measuring method
    53.
    发明授权
    Spray distribution measuring device and measuring method 有权
    喷雾分布测量装置及测量方法

    公开(公告)号:US6053037A

    公开(公告)日:2000-04-25

    申请号:US141111

    申请日:1998-08-27

    摘要: A spray distribution measuring device comprises a chamber 4 having a spray nozzle 1 as a measurement object at the top; a saucer 3 arranged below the spray nozzle within the chamber 4 and partitioned into a plurality of regions each having a prescribed area; measuring tubes 6 each installed substantially vertically from each region of the saucer 3 and having a prescribed sectional area, the upper end of each of which opens into the bottom of each region of the saucer; pressure sensors 7 each installed at the lower end of each of the measuring tubes to measure the head pressure of each measuring tube; and a controller 10 for computing a difference between the pressure applied to the pressure sensor and an initial pressure, and measures the spray distribution on the basis of a difference between the head pressure of the a test solution accumulated in each measuring tube by spraying and the initial pressure before the spraying.

    摘要翻译: 喷雾分配​​测量装置包括:在顶部具有作为测量对象的喷嘴1的腔室4; 托盘3,其布置在腔室4内的喷雾喷嘴下方,并分隔成多个具有规定面积的区域; 测量管6各自基本垂直地安装在托盘3的每个区域上并且具有规定的截面积,每个开口的上端通向托盘的每个区域的底部; 每个测量管的下端安装有压力传感器7,以测量每个测量管的头部压力; 以及控制器10,用于计算施加到压力传感器的压力与初始压力之间的差异,并且基于通过喷射在每个测量管中累积的测试溶液的头部压力与第一喷射量之间的差异来测量喷雾分布 喷涂前的初始压力。

    Analog/digital converter and voltage comparator capable of fast
producing of output offset voltage
    54.
    发明授权
    Analog/digital converter and voltage comparator capable of fast producing of output offset voltage 失效
    模拟/数字转换器和电压比较器能够快速产生输出失调电压

    公开(公告)号:US5966088A

    公开(公告)日:1999-10-12

    申请号:US982279

    申请日:1997-12-01

    IPC分类号: H03M1/44 H03M1/10 H03M1/16

    CPC分类号: H03M1/1023 H03M1/168

    摘要: An A/D converter includes a sample-hold circuit, A/D converting stages connected in series to the sample-hold circuit, and an encoder/latch circuit which adds 3-bit digital signals issued from the A/D converting stages to each other for outputting a signal of 9 bits. The sample-hold circuit and the A/D converting stages each include a differential amplifier. Differential outputs of each differential amplifier are short-circuited for a predetermined initial period in each sampling period.

    摘要翻译: A / D转换器包括采样保持电路,与采样保持电路串联连接的A / D转换级,以及编码器/锁存电路,其将从A / D转换级发出的3位数字信号加到每个 另一个用于输出9位的信号。 采样保持电路和A / D转换级各自包括差分放大器。 在每个采样周期中,每个差分放大器的差分输出在预定的初始周期短路。

    Voltage comparator and pipeline type A/D converter
    55.
    发明授权
    Voltage comparator and pipeline type A/D converter 失效
    电压比较器和流水线型A / D转换器

    公开(公告)号:US5696511A

    公开(公告)日:1997-12-09

    申请号:US738585

    申请日:1996-10-29

    CPC分类号: H03M1/0695 H03M1/167

    摘要: In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.

    摘要翻译: 在流水线型A / D转换器中,第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样,并在第一阶段输出偏移电压,并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压,并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响,使得允许高精度的A / D转换。

    Two input-two output differential latch circuit
    56.
    发明授权
    Two input-two output differential latch circuit 失效
    两路输入二输出差分锁存电路

    公开(公告)号:US5625308A

    公开(公告)日:1997-04-29

    申请号:US557556

    申请日:1995-11-14

    摘要: A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.

    摘要翻译: 一种高性能差分锁存电路,包括由用作恒流源的NMOS晶体管(27),PMOS晶体管(3,4)和NMOS晶体管(23,24)组成的差分放大器电路,由NMOS 晶体管(25,26)以及由NMOS晶体管(21,22,28)组成的用于交替操作差分放大功能和锁存功能的开关电路,用作恒流源的晶体管(27)具有直接连接的漏极端子 到晶体管(23,24)和直接连接到接地电压(2)的源极端子,由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。

    Idling revolution number control valve for an internal combustion engine
    57.
    发明授权
    Idling revolution number control valve for an internal combustion engine 失效
    用于内燃机的空转转数控制阀

    公开(公告)号:US5261371A

    公开(公告)日:1993-11-16

    申请号:US5180

    申请日:1993-01-15

    IPC分类号: F02M3/07 F02M3/00

    CPC分类号: F02M3/07

    摘要: An idling speed control valve for an internal combustion engine is disposed bypassing a throttle valve arranged at an intake passage of the engine, and proportionally controls the quantity of air flowing in the bypass passage based on an output of an electronic control unit including an idling revolution number control function. The valve is controlled by an electromagnetic coil of a solenoid device, and the coil is made of a brass series alloy wire material.

    摘要翻译: 内燃机的怠速调速阀配置在旁通配置在发动机的进气通路处的节流阀的旁边,并且根据包括怠速转数的电子控制单元的输出成比例地控制在旁路通路中流动的空气量 数控功能。 阀由螺线管装置的电磁线圈控制,线圈由黄铜系列合金线材制成。

    Method of making an idle position detection switch for engines
    58.
    发明授权
    Method of making an idle position detection switch for engines 失效
    制造发动机空转位置检测开关的方法

    公开(公告)号:US5228187A

    公开(公告)日:1993-07-20

    申请号:US961860

    申请日:1992-10-16

    IPC分类号: F02D9/02 H01H11/00 H01H13/18

    摘要: An idle position detection switch, in which a fixed contact, a terminal for transmitting an idle position signal to an external terminal, and a support disc firmly attaching both the fixed contact and the terminal are insert-molded into a connector made of a resin. As a result of the construction, not only the switch can be fabricated with less components and less cost, but also each contact portion has such an improved rigidity as to allow the incidence of false contacts to be reduced.

    摘要翻译: 一个空转位置检测开关,其中固定触点,用于将空转位置信号传送到外部端子的端子和牢固地连接固定触点和端子的支撑盘被嵌入模制到由树脂制成的连接器中。 作为结构的结果,不仅可以以更少的部件和更低的成本制造开关,而且每个接触部分都具有这样的改进的刚性,以便减少错误接触的发生。

    Potential detecting circuit
    59.
    发明授权
    Potential detecting circuit 失效
    电位检测电路

    公开(公告)号:US5208488A

    公开(公告)日:1993-05-04

    申请号:US937452

    申请日:1992-08-31

    摘要: A potential detecting circuit comprises a first MOS transistor of a first conductivity type whose drain receives an input potential that is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor of the first conductivity type whose source is connected to the second MOS transistor, source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.

    摘要翻译: 电位检测电路包括第一导电类型的第一MOS晶体管,其漏极接收绝对值比绝对值高于第一电位的第二电位的绝对值等于或等于的输入电位,第二MOS 第二导电类型的晶体管,其源极连接到第一晶体管和栅极的源极接收第一电位,源极连接到第二MOS晶体管的第一导电类型的第三MOS晶体管接收参考电位,绝对值 值低于第一电位,栅极接收第一电位;检测电位控制块,用于向第一MOS晶体管施加根据输入电位变化的电位;以及电位检测输出端,用于提供检测电位 电位检测输出端子是第二和第三MOS晶体管的漏极之间的结点。

    Semiconductor memory device having monitoring function
    60.
    发明授权
    Semiconductor memory device having monitoring function 失效
    具有监控功能的半导体存储器件

    公开(公告)号:US5179537A

    公开(公告)日:1993-01-12

    申请号:US642526

    申请日:1991-01-17

    申请人: Osamu Matsumoto

    发明人: Osamu Matsumoto

    CPC分类号: G11C16/24 G11C16/34

    摘要: Memory cells providing a memory cell array are each fromed of a floating gate MOS transistor for storing data and a select MOS transistor and the memory cell is connected to a power source via a MOS transistor providing a load element. A potential on the connection node A between the load element and the memory cell is detected by an inverter providing a potential detection circuit and a monitor output is derived from the inverter. A load providing MOS transistor having a source connected to the source of the MOS transistor providing the load element and a gate connected to the gate of the MOS transistor providing the load element is provided, a pad to which a control voltage is supplied is connected to the drain of the MOS transistor and the control voltage from the pad is applied to the gates of the MOS transistors to provide a current mirror circuit.