公开(公告)号：US20200227625A1

公开(公告)日：2020-07-16

申请号：US16261524

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC: H01L43/02 ,  H01L27/22

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US20180174970A1

公开(公告)日：2018-06-21

申请号：US15894940

申请日：2018-02-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang

IPC: H01L23/535 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.

公开(公告)号：US20180130742A1

公开(公告)日：2018-05-10

申请号：US15863986

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

公开(公告)号：US20170287843A1

公开(公告)日：2017-10-05

申请号：US15091562

申请日：2016-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Ying-Cheng Liu ,  Ching-Wen Hung ,  Yi-Hui Lee ,  Chih-Sen Huang

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/53266 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L27/092

Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.

公开(公告)号：US20170162449A1

公开(公告)日：2017-06-08

申请号：US15434067

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L21/8238 ,  H01L27/11 ,  H01L23/535 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

公开(公告)号：US20170047251A1

公开(公告)日：2017-02-16

申请号：US14824091

申请日：2015-08-12

Applicant: United Microelectronics Corp.

Inventor： Yi-Hui Lee ,  Kun-Ju Li ,  Wei-Cyuan Lo ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract translation: 一种制造半导体器件的方法包括：提供具有有源区的半导体; 在半导体上沉积介电层; 在介电层上形成图案化的蚀刻掩模; 在介电层和图案化的蚀刻掩模上沉积另外的介电层; 平面化另外的介电层，直到图案化的蚀刻掩模曝光; 以及形成另一图案化的蚀刻掩模，其在所述另外的电介质层上具有开口，使得所述图案化蚀刻掩模的部分从所述开口露出。

公开(公告)号：US20160379931A1

公开(公告)日：2016-12-29

申请号：US15257921

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

Abstract translation: 公开了半导体器件的制造方法。 首先，提供基板，其中基板包括第一金属栅极和第二金属栅极，第一金属栅极上的第一硬掩模和第二金属栅极上的第二硬掩模，以及第一层间电介质（ILD ）层围绕第一金属栅极和第二金属栅极。 接下来，将第一硬掩模和第二硬掩模用作掩模以去除用于形成凹部的第一ILD层的一部分，并且在凹部中形成图案化金属层，其中图案化金属层的顶表面为 低于第一硬掩模和第二硬掩模的顶表面。

公开(公告)号：US09530778B1

公开(公告)日：2016-12-27

申请号：US14834439

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract translation: 具有金属栅极的半导体器件包括衬底，其上形成的第一nFET器件和形成在其上的第二nFET器件。 第一nFET器件包括第一n型金属栅极，并且第一n型金属栅极包括第三底部阻挡金属层和n型功函数金属层。 n型功函数金属层直接接触第三底层阻挡层。 第二nFET器件包括第二n型金属栅极，第二n型金属栅极包括第二底部阻挡金属层，n型功函数金属层和夹在第二底部阻挡金属之间的第三p型功函数金属层 层和n型功函数金属层。 第二nFET器件的第三p型功函数金属层和第一nFET器件的第三底阻挡金属层包括相同的材料。

公开(公告)号：US09466521B2

公开(公告)日：2016-10-11

申请号：US14494607

申请日：2014-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/70 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的第一金属栅极; 第一个金属门上的第一个硬掩模; 在第一金属栅极的顶部和周围的层间绝缘层（ILD）层; 以及嵌入ILD层中的图案化金属层，其中图案化金属层的顶表面比第一硬掩模的顶表面低。

公开(公告)号：US09455227B1

公开(公告)日：2016-09-27

申请号：US14935456

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一栅极结构; 形成与所述第一栅极结构相邻的第一接触插塞; 并执行替换金属栅极（RMG）处理，以将第一栅极结构转换成金属栅极。