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    Semiconductor device with embedded cell and method of manufacturing the same
    54.
    发明授权
    Semiconductor device with embedded cell and method of manufacturing the same 有权
    具有嵌入式电池的半导体器件及其制造方法

    公开(公告)号：US09595588B1

    公开(公告)日：2017-03-14

    申请号：US15069331

    申请日：2016-03-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Sung Huang ,  Ko-Chi Chen ,  Shen-De Wang

    IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11531

    Abstract: A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.

    Abstract translation: 提供具有嵌入式单元的半导体器件。 硅衬底具有具有至少一个第一单元的第一区域和具有至少一个第二单元的第二区域。 第一单元被定位在第一区域中并形成在硅衬底的沟槽中，并且第二单元被定位在第二区域中并形成在硅衬底上。 第一单元包括形成在沟槽的侧壁和底部上的第一介电层，形成在第一介电层上并嵌入在沟槽中的浮置栅极，形成在浮置栅极上并嵌入沟槽中的第二介电层，以及 控制栅极形成在第二介电层上并嵌入在沟槽中，其中控制栅极通过第二介电层与浮置栅极分离。

    Non-volatile memory and fabricating method thereof
    55.
    发明授权
    Non-volatile memory and fabricating method thereof 有权
    非易失性存储器及其制造方法

    公开(公告)号：US09589977B1

    公开(公告)日：2017-03-07

    申请号：US14963833

    申请日：2015-12-09

    Applicant: United Microelectronics Corp.

    Inventor： Ko-Chi Chen ,  Shen-De Wang

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/28

    CPC classification number: H01L27/1157 ,  H01L21/28088 ,  H01L21/28282 ,  H01L29/408 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

    Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.

    Abstract translation: 本发明提供了一种非易失性存储器及其制造方法。 非易失性存储器包括衬底，嵌入式电荷存储晶体管和选择晶体管。 基板有开口。 嵌入式电荷存储晶体管设置在基板中。 嵌入式电荷存储晶体管包括电荷存储结构和导电层。 电荷存储结构设置在开口中的基板上。 导电层设置在电荷存储结构上并填充开口。 选择晶体管设置在嵌入式电荷存储晶体管的一侧的衬底上，其中选择晶体管包括金属栅极结构。 非易失性存储器具有优异的电荷存储容量。

    Flash cell and forming process thereof
    56.
    发明授权
    Flash cell and forming process thereof 有权
    闪电池及其成型工艺

    公开(公告)号：US09455322B1

    公开(公告)日：2016-09-27

    申请号：US14862118

    申请日：2015-09-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Weichang Liu ,  Wei Ta ,  Zhen Chen ,  Wang Xiang

    IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/788 ,  H01L27/115 ,  H01L29/51

    CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

    Abstract translation: 闪光单元形成工艺包括以下步骤。 在基板上形成第一栅极。 第一间隔件形成在第一栅极的一侧，其中第一间隔件包括底部和顶部。 底部被去除，从而形成底切。 在第一间隔物旁边形成第一选择栅，并填入底切。 本发明还提供了一种由所述闪存单元形成工艺形成的闪光单元。 闪存单元包括第一栅极，第一间隔物和第一选择栅极。 第一栅极设置在基板上。 第一间隔件设置在第一栅极的一侧，其中第一间隔件在底部具有底切，因此露出基板。 第一选择栅设置在第一间隔物旁边并延伸到底切中。

    Split gate non-volatile memory device and method for fabricating the same
    57.
    发明授权
    Split gate non-volatile memory device and method for fabricating the same 有权
    分闸非易失性存储器件及其制造方法

    公开(公告)号：US09379128B1

    公开(公告)日：2016-06-28

    申请号：US14809342

    申请日：2015-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

    IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

    CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

    Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

    Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。

    SEMICONDUCTOR STRUCTURE AND LAYOUT STRUCTURE FOR MEMORY DEVICES
    58.
    发明申请
    SEMICONDUCTOR STRUCTURE AND LAYOUT STRUCTURE FOR MEMORY DEVICES 有权
    存储器件的半导体结构和布局结构

    公开(公告)号：US20150206894A1

    公开(公告)日：2015-07-23

    申请号：US14158875

    申请日：2014-01-20

    Applicant: United Microelectronics Corp.

    Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

    IPC: H01L27/115 ,  H01L23/00

    CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

    Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。

    METHOD OF MANUFACTURING MEMORY CELL
    59.
    发明申请
    METHOD OF MANUFACTURING MEMORY CELL 审中-公开
    制造记忆细胞的方法

    公开(公告)号：US20150200279A1

    公开(公告)日：2015-07-16

    申请号：US14153069

    申请日：2014-01-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shen-De Wang

    IPC: H01L29/66 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/28 ,  H01L21/311

    CPC classification number: H01L29/66833 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518

    Abstract: A method of manufacturing a memory cell is provided. First, a substrate is provided. A patterned dielectric layer and a patterned first conductive layer are formed on the substrate. Then, a charge trapping structure and a main gate are formed on a sidewall of the patterned dielectric layer and the patterned first conductive layer. A portion of the patterned first conductive layer and a portion of the patterned dielectric layer are removed until exposing the substrate. Next, at least a source/drain region is formed in the substrate.

    Abstract translation: 提供一种制造存储单元的方法。 首先，提供基板。 图案化的介电层和图案化的第一导电层形成在衬底上。 然后，在图案化电介质层和图案化的第一导电层的侧壁上形成电荷俘获结构和主栅极。 图案化的第一导电层的一部分和图案化的介电层的一部分被去除直到暴露衬底。 接下来，至少在衬底中形成源极/漏极区域。

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