公开(公告)号：US20120044752A1

公开(公告)日：2012-02-23

申请号：US13285182

申请日：2011-10-31

申请人： Brent Keeth ,  Pierre C. Fazan

发明人： Brent Keeth ,  Pierre C. Fazan

IPC分类号： G11C11/24

CPC分类号： H01L27/10888 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10811

摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.

摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取。 存储器阵列中的至少一个包含至少100平方微米的具有至少128个功能和可操作寻址的存储器单元的连续管芯表面区域。 更优选地，至少100平方微米的连续管芯表面区域具有至少170个功能和可操作寻址的存储器单元。

公开(公告)号：US20100149855A1

公开(公告)日：2010-06-17

申请号：US12713673

申请日：2010-02-26

申请人： Brent Keeth ,  Pierre C. Fazan

发明人： Brent Keeth ,  Pierre C. Fazan

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： H01L27/10888 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10811

摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域， 功能和可操作寻址的存储器单元，更优选至少100平方微米的具有至少170个功能和可操作寻址的存储单元的连续管芯表面区域。

公开(公告)号：US07452760B2

公开(公告)日：2008-11-18

申请号：US11644863

申请日：2006-12-21

申请人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

IPC分类号： H01L21/00

CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。

公开(公告)号：US07009232B2

公开(公告)日：2006-03-07

申请号：US09915508

申请日：2001-07-26

申请人： Brent Keeth ,  Pierre C. Fazan

发明人： Brent Keeth ,  Pierre C. Fazan

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/105 ,  H01L27/108 ,  H01L27/10811 ,  Y10T29/49121

摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 根据本发明的方面，对于用于4M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。 此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个 功能和可操作地寻址的存储单元。

公开(公告)号：US06930039B2

公开(公告)日：2005-08-16

申请号：US10614916

申请日：2003-07-07

申请人： Paul J. Schuele ,  Pierre C. Fazan

发明人： Paul J. Schuele ,  Pierre C. Fazan

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in a thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer.

摘要翻译： 本发明是一种在制造在硅晶片上的动态随机存取存储器中，在形成于厚电介质层的多晶硅插塞的上表面和铂下电容器板之间形成有效的氮化钛阻挡层的工艺。

公开(公告)号：US06900493B2

公开(公告)日：2005-05-31

申请号：US10305312

申请日：2002-11-26

申请人： Brent Keeth ,  Pierre C. Fazan

发明人： Brent Keeth ,  Pierre C. Fazan

IPC分类号： H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/108 ,  H01L27/10811 ,  Y10T29/49121

摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. Considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M, and 256M integration levels. Further, an integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.

摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 对于4M，16M，64M和256M集成度的6英寸，8英寸和12英寸晶圆，可实现每片晶圆数量更多的裸片。 此外，集成电路包括半导体管芯，布置在形成在半导体管芯上的至少一个阵列中的多个功能和可操作地寻址的存储器单元，以及形成在半导体管芯上并耦合到存储器单元以允许写入数据的电路 从存储器单元读取并且从存储器单元读取，其中模具的100平方微米的连续表面积的至少一个区域具有至少170个存储单元。

公开(公告)号：US06762924B2

公开(公告)日：2004-07-13

申请号：US10321782

申请日：2002-12-17

申请人： Pierre C. Fazan ,  Gurtej S. Sandhu

发明人： Pierre C. Fazan ,  Gurtej S. Sandhu

IPC分类号： H01G101

CPC分类号： H01L27/11502 ,  H01L21/76849 ,  H01L21/7687 ,  H01L21/76889 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode having a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.

摘要翻译： 本发明是一种存储单元电容器和一种用于形成具有存储节点电极的存储单元电容器的方法，所述存储节点电极具有介于导电插塞和抗氧化层之间的阻挡层。 厚的绝缘层在具有高介电常数的介电层的沉积和退火期间保护阻挡层的侧壁。 该方法包括在诸如氧化物或氧化物/氮化物的绝缘材料的厚层中形成导电插塞。 导电插塞从厚绝缘层的平坦化顶表面凹陷。 然后在凹部中形成阻挡层。 该过程继续形成第二绝缘层，其一部分被去除以形成暴露阻挡层的一部分的开口。 在凹部中沉积抗氧化导电层，并形成电容器的存储节点电极的至少一部分。 接下来，形成具有高介电常数的电介质层，以覆盖存储节点电极，并且将电池板电极制造成过度的电介质层。

公开(公告)号：US06762450B2

公开(公告)日：2004-07-13

申请号：US09876102

申请日：2001-06-06

申请人： Gurtej Sandhu ,  Pierre C. Fazan

发明人： Gurtej Sandhu ,  Pierre C. Fazan

IPC分类号： H01L27108

CPC分类号： H01L28/87 ,  H01L27/10855

摘要： A method of forming a capacitor includes, a) providing a node to which electrical connection to a first capacitor plate is to be made; b) then, providing a finned lower capacitor plate in ohmic electrical connection with the node using no more than one photomasking step; and c) providing a capacitor dielectric layer and a conductive second capacitor plate layer over the conductive layer. Such is preferably accomplished by, i) providing a layer of conductive material outwardly of the node; ii) providing a first masking layer over the conductive material layer; iii) etching a first opening into the first masking layer over the node; iv) providing a second masking layer over the first masking layer to a thickness which less than completely fills the first opening; v) anisotropically etching the second masking layer to define a spacer received laterally within the first opening and thereby defining a second opening relative to the first masking layer which is smaller than the first opening; vi) after said anisotropically etching, etching unmasked first masking layer material away; vii) after said anisotropically etching, etching through the conductive material layer to extend the second opening to the node, the node and conductive layer being electrically isolated from one another after the conductive material layer etching; viii) plugging the extended second opening with an electrically conductive plugging material, the plugging material electrically interconnecting the node and conductive layer. Novel capacitor constructions are also disclosed.

摘要翻译： 形成电容器的方法包括：a）提供要与第一电容器板电连接的节点; b）然后，使用不超过一个光掩模步骤，在与节点的欧姆电连接中提供翅片式下电容器板; 以及c）在所述导电层上方提供电容器介电层和导电的第二电容器板层。 这样做最好通过以下方式实现：i）在节点外部提供一层导电材料; ii）在导电材料层之上提供第一掩模层; iii）在节点上蚀刻进入第一掩模层的第一开口; iv）在所述第一掩模层之上提供第二掩蔽层至小于完全填充所述第一开口的厚度; v）各向异性蚀刻所述第二掩模层以限定在所述第一开口内横向收纳的间隔件，从而限定相对于所述第一掩蔽层小于所述第一开口的第二开口; vi）在所述各向异性蚀刻之后，将未掩蔽的第一掩模层材料蚀刻掉; vii）在所述各向异性蚀刻之后，通过导电材料层蚀刻以将第二开口延伸到节点，在导电材料层蚀刻之后，节点和导电层彼此电隔离; viii）用导电堵塞材料堵塞延伸的第二开口，所述封堵材料电连接所述节点和导电层。 还公开了新颖的电容器结构。

公开(公告)号：US06589867B2

公开(公告)日：2003-07-08

申请号：US09944436

申请日：2001-08-31

申请人： Paul J. Schuele ,  Pierre C. Fazan

发明人： Paul J. Schuele ,  Pierre C. Fazan

IPC分类号： H01L214763

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in a thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer.

摘要翻译： 本发明是一种在制造在硅晶片上的动态随机存取存储器中，在形成于厚电介质层的多晶硅插塞的上表面和铂下电容器板之间形成有效的氮化钛阻挡层的工艺。

公开(公告)号：US06580114B1

公开(公告)日：2003-06-17

申请号：US09497935

申请日：2000-02-04

申请人： Thomas M Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

发明人： Thomas M Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

摘要： Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

摘要翻译： 描述形成电容器的电容器和方法。 根据一个实施方案，在衬底节点位置上形成电容器开口。 随后在电容器开口内形成导电材料，并与节点位置进行电连接。 在电容器开口内形成突出的绝缘结构，并且包括一个侧面外表面，其外表面的至少一部分由邻近的导电材料支撑并向下垂直延伸。 第一和第二电容器板及其之间的电介质层形成在电容器开口内并由突出结构支撑。 在一个方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突起结构基本上如果不是完全填充在空隙中。 另一方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突出结构仅部分地填充在空隙中以提供管状结构。