公开(公告)号：US20060087887A1

公开(公告)日：2006-04-27

申请号：US11235206

申请日：2005-09-27

申请人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

发明人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

IPC分类号： G11C16/06

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US20060072359A1

公开(公告)日：2006-04-06

申请号：US11196445

申请日：2005-08-04

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A semiconductor memory device disclosed herein includes: a first select gate line, a gate electrode of a first select transistor connected to the first select gate line; a second select gate line, a gate electrode of a second select transistor connected to the second select gate line; and word lines between the first select gate line and the second select gate line, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is adjacent to the first select gate line is read, a voltage of the second select gate line is increased after a voltage of the first select gate line is increased, and when data in a memory cell connected to a second adjacent word line adjacent to the second select gate line is read, the voltage of the first select gate line is increased after the voltage of the second gate line is increased.

摘要翻译： 本文公开的半导体存储器件包括：第一选择栅极线，连接到第一选择栅极线的第一选择晶体管的栅电极; 第二选择栅极线，连接到第二选择栅极线的第二选择晶体管的栅电极; 和第一选择栅极线与第二选择栅极线之间的字线，存储单元的栅电极分别连接到字线，其中当连接到与第一选择栅极相邻的第一相邻字线的存储单元中的数据时 在第一选择栅极线的电压增加之后第二选择栅极线的电压被增加，并且当连接到与第二选择栅极线相邻的第二相邻字线的存储单元中的数据被读取时，第二选择栅极线的电压被增加 在第二栅极线的电压增加之后第一选择栅极线的电压增加。

公开(公告)号：US20050105335A1

公开(公告)日：2005-05-19

申请号：US10944910

申请日：2004-09-21

申请人： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C5/06 ,  G11C8/10 ,  G11C8/12 ,  G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C16/08

摘要： A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.

摘要翻译： 一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元 排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。

公开(公告)号：US06839283B1

公开(公告)日：2005-01-04

申请号：US10692799

申请日：2003-10-27

申请人： Takuya Futatsuyama ,  Koji Hosono

发明人： Takuya Futatsuyama ,  Koji Hosono

IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A non-volatile semiconductor memory device, comprising a memory cell array including a plurality of electrically erasable programmable non-volatile memory cells arrayed and divided into a plurality of blocks; a plurality of word lines arranged in each of the plurality of blocks and each commonly connected to memory cells on an identical row; a plurality of drive lines provided corresponding to the plurality of word lines and each arranged to supply a voltage to the corresponding word line; a plurality of transfer transistors each operative as a switch to connect the corresponding word line to the corresponding drive line among the plurality of word lines and the plurality of drive lines, wherein said plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than said arbitrary word line and the secondary adjacent word lines, and wherein among the plurality of transfer transistors, transfer transistors for the residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for the arbitrary word line.

摘要翻译： 一种非易失性半导体存储器件，包括一个存储单元阵列，该存储单元阵列包括排列并分成多个块的多个电可擦除可编程非易失性存储单元; 多个字线布置在多个块中的每一个中并且各自共同地连接到同一行上的存储器单元; 多个驱动线，与所述多个字线对应地设置，各驱动线被配置为向对应的字线提供电压; 多个传输晶体管，各自用作开关，用于将对应的字线连接到多个字线和多个驱动线中的对应的驱动线，其中所述多个字线被分类为任意确定的任意字线， 位于与任意字线相邻的两条字线相邻的次级相邻字线以及除所述任意字线和次级相邻字线以外的剩余字线，其中，在所述多个转移晶体管中，残留字线 布置在两个相邻位置处，并且在用于任意字线的传输晶体管周围的相对位置。

公开(公告)号：US06337807B2

公开(公告)日：2002-01-08

申请号：US09749737

申请日：2000-12-28

申请人： Takuya Futatsuyama ,  Kenichi Imamiya ,  Tamio Ikehashi

发明人： Takuya Futatsuyama ,  Kenichi Imamiya ,  Tamio Ikehashi

IPC分类号： G11C1604

CPC分类号： G11C16/08

摘要： A first transistor is connected between the gates of select transistors connected to two ends of a memory cell and a select line control circuit. A first gate line is connected to the gate of the first transistor. A first voltage control circuit controls the voltage of the first gate line to turn on or off the first transistor. A second transistor is connected between the control gate of the memory cell and a word line control circuit. A second gate line separated from the first gate line is connected to the gate of the second transistor. A second voltage control circuit controls the voltage of the second gate line to turn on or off the second transistor.

摘要翻译： 第一晶体管连接在连接到存储单元的两端的选择晶体管的栅极和选择线控制电路之间。 第一栅极线连接到第一晶体管的栅极。 第一电压控制电路控制第一栅极线的电压以接通或关断第一晶体管。 第二晶体管连接在存储单元的控制栅极和字线控制电路之间。 与第一栅极线分离的第二栅极线连接到第二晶体管的栅极。 第二电压控制电路控制第二栅极线的电压以接通或关闭第二晶体管。

公开(公告)号：US08711634B2

公开(公告)日：2014-04-29

申请号：US13335095

申请日：2011-12-22

申请人： Takuya Futatsuyama ,  Takeshi Kamigaichi

发明人： Takuya Futatsuyama ,  Takeshi Kamigaichi

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483

摘要： During data read process, a control circuit gives a read voltage to a selected word line connected to a selected memory cell, and gives read pass voltages, for turning on memory cells, to unselected word lines connected to unselected memory cells. The control circuit respectively gives a first read pass voltage, a second read pass voltage, and a third read pass voltage to a first unselected word line adjacent to the selected word line at a side of at least one of a bit line and a source line, a second unselected word line adjacent to the first unselected word line at a side opposite to the selected word line, and a third unselected word line adjacent to the second unselected word line at a side opposite to the selected word line. The second read pass voltage is higher than the third read pass voltage.

摘要翻译： 在数据读取处理期间，控制电路给连接到所选择的存储单元的选定字线提供读取电压，并将用于接通存储器单元的读取通过电压提供给未选择的与未选择存储单元相连的字线。 所述控制电路分别向位于所述选择字线的位线和源极线以下的一侧的所述第一非选择字线提供第一读通过电压，第二读通过电压和第三读通过电压 ，与所选择的字线相对的一侧与第一未选字线相邻的第二未选择字线和与所选字线相对的一侧与第二未选择字线相邻的第三未选字线。 第二读取通过电压高于第三读取通过电压。

公开(公告)号：US08472259B2

公开(公告)日：2013-06-25

申请号：US13175176

申请日：2011-07-01

申请人： Takuya Futatsuyama ,  Mitsuaki Honma

发明人： Takuya Futatsuyama ,  Mitsuaki Honma

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device according to an embodiment includes a data write portion, the data write portion includes, in a write loop, a first operation mode of sequentially performing a program operation and a first verify operation, and a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation, and the data write portion includes, in the first verify operation, precharging a bit-line connected to the first memory cell and a bit-line connected to a second memory cell adjacent to the first memory cell and verifying data of the first memory cell, then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell, precharging the bit-line connected to the first memory cell and verifying data of the first memory cell.

摘要翻译： 根据实施例的非易失性半导体存储器件包括数据写入部分，数据写入部分在写入循环中包括顺序地执行编程操作和第一校验操作的第一操作模式和第二操作模式 顺序地执行编程操作，第一验证操作和第二验证操作，并且数据写入部分在第一验证操作中包括对连接到第一存储器单元的位线和连接到第二存储器单元的位线进行预充电 与所述第一存储单元相邻并且验证所述第一存储器单元的数据，则在所述第二验证操作中，当对所述第二存储单元的写入完成时，在不预先充电连接到所述第二存储单元的位线的情况下， 位线连接到第一存储器单元并且验证第一存储器单元的数据。

公开(公告)号：US08315104B2

公开(公告)日：2012-11-20

申请号：US12491638

申请日：2009-06-25

申请人： Takuya Futatsuyama ,  Toshiaki Edahiro ,  Norihiro Fujita ,  Fumitaka Arai ,  Tohru Maruyama ,  Masaki Kondo

发明人： Takuya Futatsuyama ,  Toshiaki Edahiro ,  Norihiro Fujita ,  Fumitaka Arai ,  Tohru Maruyama ,  Masaki Kondo

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C16/0483

摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

摘要翻译： 非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作 在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压 验证操作。

公开(公告)号：US08178861B2

公开(公告)日：2012-05-15

申请号：US12565439

申请日：2009-09-23

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： H01L47/00 ,  G11C11/00

CPC分类号： H01L27/24 ,  G11C13/0002 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.

摘要翻译： 半导体器件由半导体衬底，由导电多晶硅构成的在半导体衬底之上堆叠的导电层以及设置在导电层之上的金属层构成。 导电层的两端分别具有延伸性。 导电层通过设置在步骤上的金属层串联连接。 串联连接的导电层包括电阻元件。

公开(公告)号：US08169824B2

公开(公告)日：2012-05-01

申请号：US12699319

申请日：2010-02-03

申请人： Masato Endo ,  Itaru Kawabata ,  Shinichi Watanabe ,  Hiroyuki Nitta ,  Takuya Futatsuyama

发明人： Masato Endo ,  Itaru Kawabata ,  Shinichi Watanabe ,  Hiroyuki Nitta ,  Takuya Futatsuyama

IPC分类号： G11C11/34

CPC分类号： H01L21/823871 ,  G11C16/0466 ,  G11C16/26 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/41725

摘要： A semiconductor device includes a first MOS transistor, second MOS transistors, first contact plugs, and a second contact plug. The first MOS transistor with a first conductivity is formed on a semiconductor substrate. The second MOS transistors with a second conductivity are formed on the semiconductor substrate. The first contact plugs has a circular planar shape. The second contact plug has an elliptical planar shape and is formed on a source or a drain in one of the second MOS transistors. The first contact plugs are formed on sources or drains in the remaining second MOS transistors and the first MOS transistor.

摘要翻译： 半导体器件包括第一MOS晶体管，第二MOS晶体管，第一接触插塞和第二接触插塞。 具有第一导电性的第一MOS晶体管形成在半导体衬底上。 具有第二导电性的第二MOS晶体管形成在半导体衬底上。 第一接触塞具有圆形平面形状。 第二接触插塞具有椭圆形平面形状，并形成在第一MOS晶体管之一的源极或漏极上。 第一接触插塞形成在剩余的第二MOS晶体管和第一MOS晶体管的源极或漏极上。