Method and apparatus for removing solder mounted electronic components
    51.
    发明授权
    Method and apparatus for removing solder mounted electronic components 失效
    用于去除焊接安装的电子部件的方法和装置

    公开(公告)号:US4934582A

    公开(公告)日:1990-06-19

    申请号:US410171

    申请日:1989-09-20

    CPC classification number: B23K1/018 H05K13/0486

    Abstract: A method and apparatus are described for the removal of solder mounted surface mount electronic components which includes the removal of old solder, broken leads, and the electronic component without damaging other devices on the substrate. A desoldering braid is shaped to cover each of the electronic component's outer lead bonds without contacting the component's base. The desoldering braid is heated and brought in contact with the bonds until the solder flows into the desoldering braid and any broken outer leads attach to the desoldering braid. Upon removal of the desoldering braid the electronic component can be lifted off the surface. The desoldered solder joints will contain a thin uniform coating of solder less than approximately 50 micro inches thick. This allows for removal and replacement of solder mounted electronic components with leads on center lines spaced less than 0.020 inches.

    Abstract translation: 描述了用于去除焊接安装的表面贴装电子部件的方法和装置,其包括去除旧焊料,断开的引线和电子部件,而不损坏基板上的其它器件。 脱焊编织物被成形为覆盖电子部件的外引线键合中的每一个,而不接触部件的基部。 脱焊编织物被加热并与粘合物接触,直到焊料流入脱焊编织物中,并且任何断裂的外引线附着到脱焊编织物上。 在去除脱焊编织物后,电子部件可以从表面上提起。 脱模的焊点将包含小于约50微英寸厚的焊料的薄均匀涂层。 这允许在距离小于0.020英寸的中心线上引线去除和更换焊接安装的电子元件。

    Method of deposition of metal into cavities on a substrate
    55.
    发明授权
    Method of deposition of metal into cavities on a substrate 失效
    将金属沉积到基底上的空腔中的方法

    公开(公告)号:US4874493A

    公开(公告)日:1989-10-17

    申请号:US174054

    申请日:1988-03-28

    Applicant: Ju-Don T. Pan

    Inventor: Ju-Don T. Pan

    CPC classification number: C23C14/046 C23C14/46 H05K3/4076

    Abstract: A process for filling cavities in a flat surface on a substrate by metal deposition which includes depositing a film of metal onto the flat surface and cavities in a substantially perpendicular direction to the surface, and simultaneously re-sputtering and deposited film on the flat surface by ion beam milling at an angle to the surface of the substrate for achieving the deposition of metal into the cavities and filling the cavities without leaving any film on the flat surface.

    Abstract translation: 一种用于通过金属沉积在基板上的平坦表面中填充空腔的方法,该方法包括:在平坦表面上沉积金属膜,并在大致垂直于该表面的方向上沉积空腔,同时通过在平坦表面上重新溅射和沉积膜 离子束铣削与衬底的表面成一定角度,以实现金属沉积到空腔中并填充空腔而不在平坦表面上留下任何膜。

    Method of making gas heat exchanger
    56.
    发明授权
    Method of making gas heat exchanger 失效
    制造气体热交换器的方法

    公开(公告)号:US4833766A

    公开(公告)日:1989-05-30

    申请号:US222489

    申请日:1988-07-21

    Abstract: A plurality of thin flat parallel positioned thermal conductive fins adapted to be connected to an object and a gas passageway passing between adjacent fins and extending between the top of the fins and opposite sides. Gas guides are positioned between adjacent fins at the center of the plurality of fins and redirect the outlet end of the passageways normal to the inlet ends of the passageways. Alternately positioned fins face in opposing directions. The fins may be integrally formed or individually formed. A thermal conductive base may be provided at the bottom of the plurality of fins for connection to an electronic package.

    Abstract translation: 多个薄平行平行放置的导热翅片,其适于连接到物体和通过相邻翅片之间的气体通道,并且在翅片的顶部和相对侧之间延伸。 气体引导件位于多个翅片中心的相邻翅片之间,并且将通道的出口端垂直于通道的入口端重新定向。 替代的翅片面向相反的方向。 翅片可以一体形成或单独形成。 可以在多个翅片的底部设置导热基座,用于连接到电子封装。

    Fluid-cooled integrated circuit package
    57.
    发明授权
    Fluid-cooled integrated circuit package 失效
    流体冷却集成电路封装

    公开(公告)号:US4758926A

    公开(公告)日:1988-07-19

    申请号:US846087

    申请日:1986-03-31

    CPC classification number: H01L23/473 H01L2924/0002

    Abstract: A package for enclosing, protecting and cooling semiconductor integrated circuit chips. The package includes a generally planar substrate with the chips positioned thereon. Signal connections are provided between at least some of the chips. A heat sink is positioned in contact with the chips and includes microchannels through which a cooling fluid flows for purposes of transferring heat generated by the chips to such fluid. Manifolds are provided to direct the fluid to and from the microchannels, and microcapillary slots may be formed on the heat sink surface adjacent the chips to receive liquid to generate attractive forces between the heat sink and chips to facilitate heat transfer. Circuitry is provided to distribute power through the package and to the chips.

    Abstract translation: 封装,保护和冷却半导体集成电路芯片的封装。 该封装包括具有位于其上的芯片的大致平面的基板。 在至少一些芯片之间提供信号连接。 散热器定位成与芯片接触,并且包括微通道,冷却流体流过该通道用于将由芯片产生的热传递到这种流体。 提供歧管以将流体引导到微通道和从微通道引导流体,并且微毛细管狭槽可以形成在与芯片相邻的散热器表面上以接收液体以在散热器和芯片之间产生吸引力以促进热传递。 提供电路以通过封装和芯片分配电力。

    Triode structure flat panel display employing flat field emission cathode
    59.
    发明授权
    Triode structure flat panel display employing flat field emission cathode 失效
    采用平场发射阴极的三极结构平板显示器

    公开(公告)号:US5548185A

    公开(公告)日:1996-08-20

    申请号:US458854

    申请日:1995-06-02

    Abstract: A flat panel display of a field emission type having a triode (three terminal) structure and useful as a device for displaying visual information is disclosed. The display includes a plurality of corresponding light-emitting anodes and field-emission cathodes, each of the anodes emitting light in response to emission from each of the corresponding cathodes, each of the cathodes including a layer of low work function material having a relatively flat emission surface which includes a plurality of distributed localized electron emission sites and a grid assembly positioned between the corresponding anodes and cathodes to thereby control emission levels to the anodes from the corresponding cathodes. In the preferred embodiment of the invention, the layer of low work function material is amorphic diamond film. The grid assembly includes a conductive layer deposited between the plurality of anodes and cathodes and over interstices between the cathodes, the conductive layer having apertures therein, the cathodes aligned with, and of the same size as, the apertures.

    Abstract translation: 公开了一种具有三极管(三端子)结构的场发射型平板显示器,并且可用作显示视觉信息的装置。 显示器包括多个对应的发光阳极和场发射阴极,每个阳极响应于每个相应阴极的发射而发光,每个阴极包括具有相对平坦的低功函数材料层 发射表面,其包括多个分布的局部电子发射位点和位于相应阳极和阴极之间的栅格组件,从而控制来自相应阴极的阳极的发射水平。 在本发明的优选实施例中,低功函数材料层是非晶金刚石膜。 栅格组件包括沉积在多个阳极和阴极之间的导电层以及阴极之间的间隙,导电层在其中具有孔,阴极与孔对准并具有与孔相同的尺寸。

    Electrical interconnect device with customizeable surface layer and
interwoven signal lines
    60.
    发明授权
    Electrical interconnect device with customizeable surface layer and interwoven signal lines 失效
    具有可定制表面层和交织信号线的电气互连装置

    公开(公告)号:US5544018A

    公开(公告)日:1996-08-06

    申请号:US227315

    申请日:1994-04-13

    Abstract: Provided is an electrical interconnect cell intermittently spaced across a substrate to form an interconnect device or structure. The interconnect device is fully customizable or programmable upon the upper surface to accommodate various electrical components and connectivity to those components. The electrical interconnect device includes a plurality of intermittently spaced first pairs of upper and lower signal lines interwoven with a plurality of intermittently spaced second pairs of upper and lower signal lines. A bonding pad is arranged between adjacent upper and lower signal line pairs and can be connected thereto with conductive links placed upon the surface layer. Each bonding pad includes one or more pad vias which extend perpendicular to the upper surface to conductive structures arranged in lower layers. Approximately one-half of the array of bonding pads are connected to potential conductors. The pairs of upper signal lines can not only be linked, but also can be cut to form a more direct routing between target locations. Moreover, the upper and lower signal lines are connected in order for traces to extend across the entire interconnect structure for ease of testability.

    Abstract translation: 提供了间隔地跨越衬底以形成互连装置或结构的电互连电池。 互连设备在上表面上是完全可定制的或可编程的,以适应各种电气部件和与这些部件的连接。 电互连装置包括多个间歇间隔的第一对上,下信号线,与多个间歇间隔的第二对上,下信号线交织。 接合焊盘布置在相邻的上部和下部信号线对之间,并且可以与放置在表面层上的导电连接件连接。 每个焊盘包括一个或多个衬垫通孔,其垂直于上表面延伸到布置在较低层中的导电结构。 大约一半的焊盘阵列连接到电位导体。 上层信号线对不仅可以链接,而且可以被切割,以在目标位置之间形成更直接的路由。 此外,上下信号线被连接以使得迹线在整个互连结构上延伸以便易于测试。

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